Samsung S5PC110 Manual page 458

S5PC110_UM
5.5.3.24 Integration Test Control Register (APC_ITSTCTRL, R/W, Address = 0xE070_006C)
APC_ITSTCTRL Bit
Reserved [7:2]
IT_OPEN [1]
IT_IPEN [0]
5.5.3.25 Integration Test Input Read or Set Registers (APC_ITSTIP1, R/W, Address = 0xE070_0070)
APC_ITSTIP1 Bit
Reserved [7]
HPM_DELAY [6:2]
_CODE[4:0]
APC_SYNC [1]
_FROM_HPM
APC_CLAMP [0]
_ACK
Undefined. Write as zero.
Integration test output enable. The reset value is zero.
1 = APC1 is in integration test mode.
0 = APC1 is in normal mode.
This control bit also drives the apc_hpm_it_en output signal.
When this signal is asserted, the HPM is set to the integration test
mode.
In this mode the primary inputs are directly connected to the primary
outputs.
Integration test input enable. The reset value is zero.
1 = APC1 is in integration test mode.
0 = APC1 is in normal mode.
Undefined. Write as zero.
In integration test mode:
write drives the hpm_delay_code inputs to the design
•
read returns the register content.
•
In normal mode:
write updates the register
•
read returns the data from the hpm_delay_code primary inputs.
•
In integration test mode:
write drives the apc_sync_from_hpm input to the design
•
read returns the register content.
•
In normal mode:
write updates the register
•
read returns the data from the apc_sync_from_hpm primary input.
•
In integration test mode:
write drives the apc_clamp_ack input to the design
•
read returns the register content.
•
In normal mode:
write updates the register
•
read returns the data from the apc_clamp_ack primary input.
•
5 INTELLIGENT ENERGY MANAGEMENT
Description
Description
Initial State
0
0
0
Initial State
0
0x00
0
0
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