Samsung S5PC110 Manual page 848

S5PC110_UM
2.5.1.5 MULTI-MASTER I
•
I2CLC0, R/W, Address = 0xE180_0010
•
I2CLC2, R/W, Address = 0xE1A0_0010
•
I2CLC_HDMI_DDC, R/W, Address = 0xFAB0_0010
•
I2CLC_HDMI_PHY, R/W, Address = 0xFA90_0010
I2CLC Bit
Filter enable
SDA output [1:0]
delay
2
C-Bus Line Control Register
2
[2]
I C-bus filter enable bit.
If SDA port is operating as input, this bit should be High. This filter
prevents error caused by glitch between two PCLK clock.
0 = Disables Filter
1 = Enables Filter
2
I C-Bus SDA line delay length selection bits.
SDA line is delayed as following clock time(PCLK)
00 = 0 clocks
01 = 5 clocks
10 = 10 clocks
11 = 15 clocks
Description
2 IIC-BUS INTERFACE
Initial State
0
00
2-16