Samsung S5PC110 Manual page 294

S5PC110_UM
2.2.60.15 External Interrupt Control Registers (EXT_INT_2_MASK, R/W, Address = 0xE020_0F08)
EXT_INT_2_MASK
Reserved
EXT_INT_2_MASK[7]
EXT_INT_2_MASK[6]
EXT_INT_2_MASK[5]
EXT_INT_2_MASK[4]
EXT_INT_2_MASK[3]
EXT_INT_2_MASK[2]
EXT_INT_2_MASK[1]
EXT_INT_2_MASK[0]
2.2.60.16 External Interrupt Control Registers (EXT_INT_3_MASK, R/W, Address = 0xE020_0F0C)
EXT_INT_3_MASK
Reserved
EXT_INT_3_MASK[7]
EXT_INT_3_MASK[6]
EXT_INT_3_MASK[5]
EXT_INT_3_MASK[4]
EXT_INT_3_MASK[3]
EXT_INT_3_MASK[2]
EXT_INT_3_MASK[1]
EXT_INT_3_MASK[0]
Bit
[31:8] Reserved
[7] 0 = Enables Interrupt
1 = Masked
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
Bit
[31:8] Reserved
[7] 0 = Enables Interrupt
1 = Masked
[6] 0 = Enables Interrupt
1 = Masked
[5] 0 = Enables Interrupt
1 = Masked
[4] 0 = Enables Interrupt
1 = Masked
[3] 0 = Enables Interrupt
1 = Masked
[2] 0 = Enables Interrupt
1 = Masked
[1] 0 = Enables Interrupt
1 = Masked
[0] 0 = Enables Interrupt
1 = Masked
2 GENERAL PURPOSE INPUT/ OUTPUT
Description
Description
Initial State
0
1
1
1
1
1
1
1
1
Initial State
0
1
1
1
1
1
1
1
1
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