Samsung S5PC110 Manual page 908

S5PC110_UM
5.8.3.2 OTG Interrupt Register (GOTGINT, R/W, Address = 0xEC00_0004)
The application reads this register at the time of OTG interrupt. To clear the OTG interrupt, application clears the
bits in this register.
GOTGINT Bit
Reserved [31:20] -
DbnceDone [19]
ADev [18]
TOUTChg
HstNegDet [17]
Reserved [16:10] -
HstnegSuc [9]
StsChng
SesReq [8]
SucStsChng
Reserved [7:3]
SesEndDet [2]
Reserved [1:0]
Debounce Done
The core sets this bit if the debounce is complete after the
device connects. This bit is valid if the HNP Capable or SRP
Capable bit is set in the Core USB Configuration register.
A-Device Timeout Change
The core sets this bit to indicate that the A-device has timed
out while waiting for the B-device to connect.
Host Negotiation Detected.
The core sets this bit if it detects a host negotiation request
on the USB.
Host Negotiation Success Status Change
The core sets this bit on the success or failure of a
USB host negotiation request.
Session Request Success Status Change
The core sets this bit on the success or failure of a session
request.
-
Session End Detected
The core sets this bit if the b_valid signal is deasserted.
-
Description
5 USB2.0 HS OTG
R/W Initial State
- 12'h0
R_SS_ 1'b0
WC
R_SS_ 1'b0
WC
R_SS_ 1'b0
WC
- 7'h0
R_SS_ 1'b0
WC
R_SS_ 1'b0
WC
- 5'h0
R_SS_ 1'b0
WC
- 2'h0
5-32