Samsung S5PC110 Manual page 321

S5PC110_UM
3.7.2.4 PLL Control Registers (VPLL_CON, R/W, Address = 0xE010_0120)
VPLL_CON
ENABLE
Reserved
LOCKED
Reserved
VSEL
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively, if the
input clock frequency is 24 MHz.
Equation to calculate the output frequency:
FOUT = MDIV X FIN / (PDIV X 2
where, MDIV, PDIV, SDIV for PLLs must meet the following conditions :
PDIV: 1 ≤ PDIV ≤ 63
MDIV: 16 ≤ MDIV ≤ 511
SDIV: 0 ≤ SDIV ≤ 5
Fref (=FIN / PDIV): 2MHz ≤ Fref ≤ 6MHz
FVCO (=MDIV X FIN / PDIV):
330MHz ≤ FVCO ≤ 460MHz when VSEL=LOW.
460MHz ≤ FVCO ≤ 660MHz when VSEL=HIGH.
FOUT : 12MHz ≤ FOUT ≤ 660MHz
Refer to
3.3.4 Recommended PLL PMS Value for VPLL
VPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop,
Caution:
sleep mode. VPLL will be automatically turned off while entering those low-power modes.
Bit
[31] PLL enable control (0: disable, 1: enable)
[30] Reserved
[29] PLL locking indication
0 = Unlocked
1 = Locked
Read Only
[28] Reserved
[27] VCO frequency range selection
[26:25] Do not change
[24:16] PLL M divide value
[15:14] Reserved
[13:8] PLL P divide value
[7:3] Reserved
[2:0] PLL S divide value
SDIV
)
Description
for recommended PMS values.
3 CLOCK CONTROLLER
Initial State
0
0
0
0
0x0
0
0x6C
0
0x3
0
0x3
3-24