Samsung S5PC110 Manual page 313

S5PC110_UM
Register
DCGIDX_MAP0
DCGIDX_MAP1
DCGIDX_MAP2
Reserved
DCGPERF_MAP0
DCGPERF_MAP1
Reserved
DVCIDX_MAP
Reserved
FREQ_CPU
FREQ_DPM
Reserved
DVSEMCLK_EN
MAXPERF
Reserved
APLL_CON0_L8
APLL_CON0_L7
APLL_CON0_L6
APLL_CON0_L5
APLL_CON0_L4
APLL_CON0_L3
APLL_CON0_L2
APLL_CON0_L1
Reserved
CLKDIV_IEM_L8
CLKDIV_IEM_L7
CLKDIV_IEM_L6
CLKDIV_IEM_L5
CLKDIV_IEM_L4
Address R/W
0xE010_3000 R/W
0xE010_3004 R/W
0xE010_3008 R/W
0xE010_300C~ -
0xE010_301C
0xE010_3020 R/W
0xE010_3024 R/W
0xE010_3028~ -
0xE010_303C
0xE010_3040 R/W
0xE010_3044~ -
0xE010_305C
0xE010_3060 R/W
0xE010_3064 R/W
0xE010_3068~ -
0xE010_307C
0xE010_3080 R/W
0xE010_3084 R/W
0xE010_3088~ -
0xE010_30FC
0xE010_3100 R/W
0xE010_3104 R/W
0xE010_3108 R/W
0xE010_310C R/W
0xE010_3110 R/W
0xE010_3114 R/W
0xE010_3118 R/W
0xE010_311C R/W
0xE010_3120~ -
0xE010_31FC
0xE010_3200 R/W
0xE010_3204 R/W
0xE010_3208 R/W
0xE010_320C R/W
0xE010_3210 R/W
Description
DCG index map 0
DCG index map 1
DCG index map 2
Reserved
DCG performance map 0
DCG performance map 1
Reserved
DVC index map
Reserved
Maximum frequence of CPU
Frequency of DPM accumulators
Reserved
DVS emulation clock enable
MAX performance enable
Reserved
APLL control (performance level-8)
APLL control (performance level-7)
APLL control (performance level-6)
APLL control (performance level-5)
APLL control (performance level-4)
APLL control (performance level-3)
APLL control (performance level-2)
APLL control (performance level-1)
Reserved
Clock divider for IEM (performance level-
8)
Clock divider for IEM (performance level-
7)
Clock divider for IEM (performance level-
6)
Clock divider for IEM (performance level-
5)
Clock divider for IEM (performance level-
3 CLOCK CONTROLLER
Reset Value
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
-
0xFFFF_FFFF
0xFFFF_FFFF
-
0x00FF_FFFF
-
0x0000_0000
0x0000_0000
-
0x0000_0000
0x0000_0000
-
0x00C8_0301
0x00C8_0301
0x00C8_0301
0x00C8_0301
0x00C8_0301
0x00C8_0301
0x00C8_0301
0x00C8_0301
-
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
3-16