Deep-Stop Mode - Samsung S5PC110 Manual

S5PC110_UM

4.3.6 DEEP-STOP MODE

In DEEP-STOP mode, Cortex-A8 Core is power-gated rather than clock-gated, and the remaining parts of the chip
are power-gated (except RTC module). However, TOP domain can either be power-on or power-gated by setting
TOP_LOGIC field of STOP_CFG register before entry into DEEP-STOP mode. Cortex-A8 L2 cache can be
powered on for memory retention or power-gated to save power.
•
TOP_LOGIC = 2'b01, TOP block is power-gated.
•
TOP_LOGIC = 2'b10, TOP block is power "ON".
To enter the DEEP-STOP mode,
1. Make sure all PLLs are running before entering low-power mode.
This can be done by checking APLL_CON0, MPLL_CON, EPLL_CON0, VPLL_CON register.
2. Cut power off for all sub-blocks (LCD, CAM, TV, 3D, MFC) and verifies it is finised.
3. Set ARM_LOGIC field of STOP_CFG register to 2'b00.
4. Set other fields of STOP_CFG based on the users' requirements.
5. Set CFG_STANDBYWFI field of PWR_CFG to 2'b10
6. Set SYSCON_INT_DISABLE field of OTHERS to 1'b1
7. Execute Wait-For-Interrupt instruction (WFI). If SYSCON_INT_DISABLE field of OTHERS is still 1'b1 after
calling wfi instruction, this indicates wfi instruction is ignored by the processor
and user should call wfi instruction again.
The SYSCON performs the following sequence to enter DEEP-STOP mode.
1. Complete all active bus transactions.
2. Complete all active memory controller transactions.
3. Allow external DRAM to enter self-refresh mode (to preserve DRAM contents).
4. Mask clock input using internal signal in SYSCON.
5. Disable all PLLs.
6. Selectively disable OSCs except 32.768KHz.
To exit the DEEP-STOP mode, wake up sources (For more information, refer to
Then SYSCON performs the following sequence to exit from DEEP-STOP mode.
1. Enable the OSC pads if disabled and wait for the OSC stabilization (around 1ms).
2. Enable the PLLs and wait for locking (about 300us).
3. Unmask clock input to clock-on blocks.
4 POWER MANAGEMENT
Section 4.6 "Wakeup Sources").
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