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In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
NMI
NMIEG
SSBY
Figure 22.2 Software Standby Mode Application Example
22.2.4
Hardware Standby Mode
Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made
to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
NMI exception
Software standby mode
handling
(power-down mode)
NMIEG=1
SSBY=1
SLEEP instruction
NMI exception
Oscillation
handling
stabilization
time t
OSC2
Rev. 2.00, 05/03, page 693 of 820
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