Hardware Standby Mode; Transition To Hardware Standby Mode; Exit From Hardware Standby Mode; Timing For Hardware Standby Mode - Renesas F-ZTAT H8 Series Hardware Manual

21.5

Hardware Standby Mode

21.5.1

Transition to Hardware Standby Mode

Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU, DMAC, refresh controller, and on-chip supporting modules. All modules are reset
except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is
retained. I/O ports are placed in the high-impedance state.
Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby
mode.
21.5.2

Exit from Hardware Standby Mode

Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
21.5.3

Timing for Hardware Standby Mode

Figure 21.2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive
STBY high, wait for the clock to settle, then bring RES from low to high.
Section 21 Power-Down State
Rev. 7.00 Sep 21, 2005 page 673 of 878
REJ09B0259-0700