Hardware Standby Mode; Transition To Hardware Standby Mode; Clearing Hardware Standby Mode; Hardware Standby Mode Timings - Renesas H8S Series Hardware Manual

20.5

Hardware Standby Mode

20.5.1

Transition to Hardware Standby Mode

When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD0 to MD2) while this LSI is in hardware standby
mode.
20.5.2

Clearing Hardware Standby Mode

Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the
oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
20.5.3

Hardware Standby Mode Timings

Timing of Transition to Hardware Standby Mode
1. To retain RAM contents with the RAME bit set to 1 in SYSCR
Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in
figure 20.4. After STBY has gone low, RES has to wait for at least 0 ns before becoming high.
STBY
RES

Figure 20.4 Timing of Transition to Hardware Standby Mode

≥ 10 t ≥ 0 ns
t t
1 cyc 2
Rev. 6.00 Mar 15, 2006 page 503 of 570
Section 20 Power-Down Modes
REJ09B0211-0600