C Bus Status Register A (Icsra); C Bus Transmit Data Register (Icdrt); C Bus Receive Data Register (Icdrr) - Renesas H8S/2437 Hardware Manual

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17.3.10 I

C Bus Status Register A (ICSRA)

ICSRA confirms slave address recognition flags.
Bit Bit Name Initial Value R/W Description
7 AASA 0
6 AASB 0
5 to 0 
All 0
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17.3.11 I

C Bus Transmit Data Register (ICDRT)

ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
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space in the I C bus shift register (ICDRS), it transfers the transmit data which is written in
ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data in ICDRS, continuous transfer is possible.
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17.3.12 I

C Bus Receive Data Register (ICDRR)

ICDRR is an 8-bit register that stores the receive data. When one byte of data is received, ICDRR
transfers the received data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore this register cannot be written to by the CPU.
R/W Slave Address Recognition Flag A
In slave receive mode, this flag is set to 1 if the upper 7 bits
in the first frame following a start condition match bits
SVA6 to SVA0 in SARA.
[Setting condition]
•
When the slave address is detected in slave receive
mode
[Clearing condition]
•
When 0 is written to AASA after reading AASA = 1
R/W Slave Address Recognition Flag B
In slave receive mode, this flag is set to 1 if the upper 7 bits
in the first frame following a start condition match bits
SVA6 to SVA0 in SARB.
[Setting condition]
•
When the slave address is detected in slave receive
mode
[Clearing condition]
•
When 0 is written to AASB after reading AASB = 1

Reserved
These bits are always read as 0.
Rev. 1.00, 09/03, page 489 of 704