Figure 6.54 Example Of Timing For Idle Cycle Insertion In Case Of Consecutive Read - Renesas H8S/2368 Series Hardware Manual

Previous Access Next Access
Normal space write Normal space read
DRAM/ space read
DRAM/ space write Normal space read
DRAM/ space read
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/ space burst access. Figures 6.54 shows an
example of the timing for idle cycle insertion in the case of consecutive read and write accesses to
DRAM/continuous synchronous DRAM space.
Address bus
Data bus
Note: n = 2, 3
Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Rev. 2.00, 05/03, page 188 of 820
DRAM space read
T
p
( )
,
( )
Write Accesses to DRAM Space in RAS Down Mode
ICIS2 ICIS1 ICIS0
0 — —
1 — —
0 — —
1 — —
0 — —
1 — —
0 — —
1 — —
DRAM space write
T T T T
r c1 c2 i
Idle cycle
DRMI IDLC Idle cycle
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
— — Disabled
— 0 1 state inserted
1 2 states inserted
T T
c1 c2