Address Error; Address Error Source; Table 4.5 Bus Cycle And Address Error - Renesas H8SX/1520 Series Hardware Manual

4.5

Address Error

4.5.1

Address Error Source

Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5
may cause an address error.
Table 4.5
Bus Cycle
Type
Instruction fetch CPU
Stack operation CPU
Data read/write CPU
Data read/write DMAC
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Bus Cycle and Address Error
Bus Master Description
Fetches instructions from even addresses
Fetches instructions from odd addresses
Fetches instructions from areas other than
on-chip peripheral module space*
Fetches instructions from on-chip peripheral
1
module space*
Fetches instructions from external memory
space in single-chip mode
Fetches instructions from access reserved
2
area.*
Accesses stack when the stack pointer value
is even address
Accesses stack when the stack pointer value
is odd
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-
chip mode
Accesses to reserved area*
Accesses word data from even addresses
Accesses word data from odd addresses
Accesses external memory space in single-
chip mode
Accesses to reserved area*
Section 4 Exception Handling
Address Error
No (normal)
Occurs
No (normal)
1
Occurs
Occurs
Occurs
No (normal)
Occurs
No (normal)
No (normal)
Occurs
2
Occurs
No (normal)
No (normal)
Occurs
2
Occurs
Rev. 3.00 Mar. 14, 2006 Page 79 of 804
REJ09B0104-0300