Instruction Cache Pins - Renesas NU85E Preliminary User's Manual

2.2.8 Instruction cache pins

(1) IBDRRQ (input)
This is the pin to which fetch requests are input from the instruction cache.
A request signal is input which fetches data from the external memory to the NU85E.
(2) IBEA25 to IBEA2 (input)
These pins constitute a bus to which fetch addresses are input from the instruction cache.
Upon a miss-hit, the address to be read is input from the instruction cache.
(3) IBAACK (output)
This is the pin from which address acknowledgements are output to the instruction cache.
This signal is output when the NU85E recognizes the IBEA25 to IBEA2 signals input from the instruction cache.
(4) IBDRDY (output)
This is the pin from which data ready signals are output to the instruction cache.
Upon an instruction cache miss-hit, when the NU85E has finished fetching the data to be read from the external
memory, this signal is output to indicate that a refill for the instruction cache is ready.
(5) IBDLE3 to IBDLE0 (output)
These are the pins from which data latch enable signals are output to the instruction cache.
(6) IBEDI31 to IBEDI0 (output)
These pins constitute a bus from which data is output to the instruction cache.
Upon an instruction cache miss-hit, the data to be refilled is output to the instruction cache.
(7) IIDRRQ (output)
This is the pin from which fetch requests are output to the instruction cache.
(8) IIEA25 to IIEA2 (output)
These pins constitute a bus from which fetch addresses are output to the instruction cache.
The address to be fetched is output from the external memory simultaneous with the fetch request (IIDRRQ).
(9) IIAACK (input)
This is the pin to which address acknowledgements are input from the instruction cache.
This signal is input to the NU85E when the instruction cache recognizes the fetch address signals (IIEA25 to
IIEA2) input from the NU85E.
(10) IIDLEF (input)
This is the pin to which data latch enable signals are input from the instruction cache.
(11) IIEDI31 to IIEDI0 (input)
These pins constitute a bus to which data is input from the instruction cache.
The data to be read is input from the instruction cache.
(12) IIBTFT (output)
This is the pin from which the branch target fetch status is output to the instruction cache.
A high level is output when a jump destination address is fetched due to a branch instruction.
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CHAPTER 2 PIN FUNCTIONS
Preliminary User's Manual A14874EJ3V0UM