Figure 2.2 Exception Vector Table (Normal Mode); Figure 2.3 Stack Structure (Normal Mode) - Renesas H8SX/1520 Series Hardware Manual

Section 2 CPU
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The structure of the exception vector table is shown in
figure 2.2.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
Rev. 3.00 Mar. 14, 2006 Page 22 of 804
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H'0000
H'0001
H'0002
H'0003

Figure 2.2 Exception Vector Table (Normal Mode)

SP
PC
(16 bits)
(a) Subroutine Branch
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored on return.

Figure 2.3 Stack Structure (Normal Mode)

Reset exception vector
Reset exception vector
SP
2
*
(SP )
Exception
vector table
1
EXR*
1 3
Reserved* ,*
CCR
3
CCR*
PC
(16 bits)
(b) Exception Handling