Figure 6.40 Example Of Dack Output Timing When Dds = 1 (Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1.
Address bus
Read
Data bus
Write
Data bus
Note: n = 2, 3
Figure 6.40 Example of DACK
When DDS = 0 : When DRAM space is accessed in DMAC single address transfer mode, full
access (normal access) is always performed. With the DRAM interface, the DACK output goes
low from the T state.
r
In modes other than DMAC single address transfer mode, burst access can be used when
accessing DRAM space.
Figure 6.41 shows the DACK output timing for the DRAM interface when DDS = 0.
Rev. 2.00, 05/03, page 174 of 820
T
p
Row address
( )
,
( )
( )
( )
( )
DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) DACK DACK
T T
r c1
Column address
High
High
T
c2