Chip Select Signals - Renesas H8S/2633 Series Hardware Manual

7.3.5

Chip Select Signals

This LSI allows chip select signals (CS0 to CS7) to be output for each of areas 0 to 7. The level of
these signals is set Low when accessing the external space of the respective area.
Figure 7-3 shows example CSn (where n=0 to 7) signal output timing.
The output of the CSn signal can be enabled or disabled by the data direction register (DDR) of
the port of the corresponding CSn pin.
In ROM-disabled expanded mode, the CS0 pin is set for output after a power-on reset. The CS1 to
CS7 pins are set for input after a power-on reset, so the corresponding DDR must be set to 1 to
allow the output of CS1 to CS7 signals.
In ROM-disabled expanded mode, all of pins CS0 to CS7 are set for input after a power-on reset,
so the corresponding DDR must be set to 1 to allow the output of CS0 to CS7 signals.
See sections 10A and 10B, I/O Ports for details.
When areas 2 to 5 are set as DRAM * space, CS2 to CS5 outputs are used as RAS signals.
Note: * DRAM interface is not available in the H8S/2695.
ø
Address bus
CSn
Figure 7-3 CSn Signal Output Timing (where n=0 to 7)
192
Bus cycle
T T
1 2
Area n external address
T
3