Clock Synchronous Serial I/O With Chip Select (Ssu) - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group
16.2

Clock Synchronous Serial I/O with Chip Select (SSU)

Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 shows a Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block
Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show Clock Synchronous Serial
I/O with Chip Select Associated Registers.
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications
Item
Transfer data format
Operating mode
Master / slave device
I/O pins
Transfer clock
Receive error detection • Overrun error
Multimaster error
detection
Interrupt requests
Select functions
NOTE:
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
• Transfer data length: 8 bits
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when the next serial data receive is completed, the ORER bit is set to 1.
• Conflict error
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if "L" applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from "L" to
"H", the CE bit in the SSSR register is set to 1.
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error).
• Data transfer direction
Selects MSB-first or LSB-first.
• SSCK clock polarity
Selects "L" or "H" level when clock stops.
• SSCK clock phase
Selects edge of data change and data download.
Page 170 of 315
16. Clock Synchronous Serial Interface
Specification
(1)