Bus Control; Address Bus; Data Bus; Chip Select Signal - Renesas M16C/62P Series Hardware Manual

M16C/62P Group (M16C/62P, M16C/62PT)
8.2

Bus Control

The following describes the signals needed for accessing external devices and the functionality of software wait.
8.2.1

Address Bus

The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by
using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the PM06 and
PM11 Bits Set Value and Address Bus Width.
Table 8.2 PM06 and PM11 Bits Set Value and Address Bus Width
(1)
Set Value
PM11=1
PM06=1
PM11=0
PM06=1
PM11=0
PM06=0
NOTES:
1. No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address bus is
indeterminate until any external area is accessed.
8.2.2

Data Bus

When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when
input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
8.2.3

Chip Select Signal

The chip select (hereafter referred to as the CSi) signals are output from the CSi (i = 0 to 3) pins. These pins
can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 8.1 shows the CSR Register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the
CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9. Memory
Space Expansion Function. Figure 8.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte
mode.
Rev.2.41 Jan 10, 2006
REJ09B0185-0241
http://www.xinpian.net
Pin Function
P3_4 to P3_7
P4_0 to P4_3
A12 to A15
P4_0 to P4_3
A12 to A15
A16 to A19
Page 60 of 390
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Address Bus Width
12 bits
16 bits
20 bits
8. Bus
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