Reset Generation According To The Condition Of Smart Option - Samsung S3F80JB User Manual

RESET
Table 8-5. Reset Generation According to the Condition of Smart Option
Mode
Reset Pin
Watch Dog Timer Enable
Normal
IPOR
Operating
LVD
External Interrupt (EI) P0 and P2
External Interrupt (DI) P0 and
P2
Reset Pin
Watch Dog Timer Enable
IPOR
Stop
Mode
LVD
External Interrupt (EI-Enable) P0
and P2
SED&R
1. 'X' means that a corresponding reset source don't generate reset signal. 'O' means that a
corresponding reset source generates reset signal.
2. 'Reset' means that reset signal is generated and chip reset occurs,
3. 'Continue' means that it executes the next instruction continuously without ISR execution.
4. 'External ISR' means that chip executes the interrupt service routine of generated external interrupt
source.
5. 'STOP ' means that the chip is in stop state.
6. 'STOP Release and External ISR' means that chip executes the external interrupt service routine of
generated external interrupt source after STOP released.
7. 'STOP Release and Continue' means that executes the next instruction continuously after STOP
released.
8-18
Reset Source
P0 & P2.4-2.7
P2.0-2.3
Smart option7th bit @3FH
1
O Reset
O Reset
X Continue
O Reset
X External ISR
X Continue
O Reset
X STOP
X STOP
O STOP Release and
Reset
X STOP Release and
External ISR
X STOP Release and
Continue
X STOP
NOTES
S3F80JB
0
O Reset
O Reset
X Continue
O Reset
X External ISR
X Continue
O Reset
X STOP
O STOP Release and
Reset
X STOP
O STOP Release and
Reset
O STOP Release and
Reset
X STOP