Table 18.4 Boot Mode Operation; Table 18.5 System Clock Frequencies For Which Automatic Adjustment Of Lsi Bit Rate Is - Renesas H8S Series Hardware Manual

Section 18 ROM

Table 18.4 Boot Mode Operation

Host Operation
Item Processing Contents
Boot mode
start
Bit rate Continuously transmits data H'00 at
adjustment specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
Receives data H'AA.
Transfer of
Transmits number of bytes (N) of
programming
programming control program to be
control
transferred as 2-byte data (low-order
program
byte following high-order byte).
Transmits 1-byte of programming
control program (repeated for
N times).
Flash memory
erase
Receives data H'AA.

Table 18.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is

Possible
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
Rev. 6.00 Mar 15, 2006 page 468 of 570
REJ09B0211-0600
Communications Contents
H'00, H'00 ...... H'00
High-order byte and
low-order byte
Boot program
erase error
System Clock Frequency Range of LSI
20 MHz
8 to 20 MHz
4 to 20 MHz
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
. Measures low-level period of receive data
H'00.
. Calculates bit rate and sets it in BRR of
SCI_2.
. Transmits data H'00 to host as adjustment
H'00
end indication.
H'55
Transmits data H'AA to host when data
H'AA
H'55 is received.
Echobacks the 2-byte data received.
Echoback
H'XX
Echobacks received data to host and also
Echoback
transfers it to RAM (repeated for N times).
Checks flash memory data, erases all
H'FF
flash memory blocks in case of written
data existing, and transmits data H'AA to
host. (If erase could not be done,
transmits data H'FF to host and aborts
H'AA
operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.