Activation By Falling Edge On Dreq Pin; Figure 7.41 Example In Which Low Level Is Not Output At Tend Pin - Renesas H8S/2368 Series Hardware Manual

4. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
Internal address
Internal read signal
Internal write signal
External address
Figure 7.41 Example in which Low Level is Not Output at TEND
Activation by Falling Edge on DREQ
7.7.5
DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and
switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and
switches to [1].
Rev. 2.00, 05/03, page 272 of 820
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DREQ Pin
DREQ DREQ
DMA
read
Not output
External write by CPU, etc.
DMA
write
TEND Pin TEND TEND