Precautions; Transmission/Reception - Renesas M16C Series User Manual

M30240 Group

2.4.3 Precautions

2.4.3.1 Transmission/Reception

With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to "L" when the data-receivable status becomes ready, which informs the transmission side that the
reception has become ready. The output level of the RTSi pin goes to "H" when reception starts. So if
the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmit and receive
data with consistent timing. With the internal clock, the RTS function has no effect. Figure 2.54 shows
an example of wiring.
Figure 2.54: Example of wiring
Transmission
With an external clock selected, perform the following set-up procedure with the CLKi pin input level
= "H" if the CLK polarity select bit = "0", or with the CLKi pin input level = "L" if the CLK polarity select
bit = "1":
1. Set the transmit enable bit (to "1")
2. Write transmission data to the UARTi transmit buffer register
3. "L" level input to the CTSi pin (when the CTS function is selected)
Reception
(1) While operating in clock-synchronous serial I/O mode, transmiting data generates a shift clock.
Configure the settings for transmission even when using the device only for reception. Dummy data
are output to the outside from the TxDi pin (transmission pin) when receiving data.
(2) With the internal clock selected, setting the transmit enable bit to "1" (transmission-enabled status)
and setting dummy data in the UARTi transmission buffer register generates a shift clock.
With the external clock selected, a shift clock is generated when the transmit enable bit is set to "1",
dummy data is set in the UARTi transmit buffer register, and the external clock is input to the CLKi pin.
(3) While receiving data in continuous mode, an overrun error occurs when the next reception data
are made ready in the UARTi receive register with the receive complete flag set to "1" (before the con-
tent of the UARTi receive buffer register is read), and overrun error flag is set to "1". In this instance,
the next data are written to the UARTi receive buffer register. To handle this problem, write software
for transmit and receive so that the previous data are retransmitted.
If an overrun error occurs, the UARTi receive interrupt request bit does not go to "1".
(4) To receive data in continuous mode, set dummy data in the lower-order byte of the UARTi transmit
buffer register every time reception is made.
Rev.1.00 Sep 24, 2003 Page 198 of 360
Transmitter side IC
TxDi
RxDi
CLKi
CTSi
Clock-Synchronous Serial I/O
Receiver side IC
TxDi
RxDi
CLKi
RTSi