Section 11 Watchdog Timer (Wdt); Features; Figure 11.1 Block Diagram Of Wdt - Renesas H8SX/1520 Series Hardware Manual

The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash
prevents the CPU from writing to the timer counter, thus allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
Figure 11.1 shows a block diagram of the WDT.
11.1

Features

• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
 In watchdog timer mode
If the counter overflows, this LSI can be initialized internally.
 In interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
(interrupt request
Internal reset signal*
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Section 11 Watchdog Timer (WDT)

Interrupt
WOVI
control
signal)
Reset
control
RSTCSR
[Legend]
Timer control/status register
TCSR:
Timer counter
TCNT:
Reset control/status register
RSTCSR:
Note: * An internal reset signal can be generated by the RSTCSR setting.

Figure 11.1 Block Diagram of WDT

Overflow
Clock
Clock
select
TCNT TCSR
Module bus
WDT
Rev. 3.00 Mar. 14, 2006 Page 367 of 804
Section 11 Watchdog Timer (WDT)
Pφ/2
Pφ/64
Pφ/128
Pφ/512
Pφ/2048
Pφ/8192
Pφ/32768
Pφ/131072
Internal clocks
Bus
interface
REJ09B0104-0300