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Section 15 Watchdog Timer (WDT)
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an
internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from
writing to the timer counter, thus allowing it to overflow.
When this watchdog timer function is not needed, the WDT can be used as an interval timer. In
interval timer operation, an interval timer interrupt is generated each time the counter overflows.
15.1
Features
• Selectable from eight counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
•
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
Interval Timer Mode:
•
If the counter overflows, an interval timer interrupt (WOVI) is generated.
A block diagram of the WDT is shown in figure 15.1.
WOVI
(Interrupt request signal)
Internal NMI
(Interrupt request signal)
Internal reset signal
[Legend]
TCSR:
Timer control/status register
TCN :
Timer counter
WDT0102A_000020020300
Interrupt
control
Overflow
Reset
control
TCNT
Module bus
Figure 15.1 Block Diagram of WDT
Clock
Clock
selection
Internal clock
TCSR
WDT
Rev. 1.00, 09/03, page 417 of 704
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Bus
interface
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