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7.1
Overview
The H8S/2633 Series has a built-in bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC)*.
Note: * This function is not available in the H8S/2695.
7.1.1
Features
The features of the bus controller are listed below.
• Manages external address space in area units
Manages the external space as 8 areas of 2-Mbytes
Bus specifications can be set independently for each area
DRAM/Burst ROM interface can be set
• Basic bus interface
Chip selects (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• DRAM interface*
DRAM interface can be set for areas 2 to 5 (in advanced mode)
Multiplexed output of row and column addresses (8/9/10-bit)
2 CAS method
Burst operation (in high-speed mode)
Insertion of T
P
Selection of CAS-before-RAS refresh and self refresh
• Burst ROM interface
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
Section 7 Bus Controller
cycle to secure RAS precharge time
165
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