Basic Bus Cycles; Dma Transfer (Dual Address Mode) Bus Cycles; Figure 7.17 Example Of Dma Transfer Bus Timing - Renesas H8S/2368 Series Hardware Manual

7.5.8

Basic Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
CPU cycle DMAC cycle (1-word transfer) CPU cycle
T T T T T T T T
1 2 1 2 3 1 2 3
Source
Destination address
address
Address bus

Figure 7.17 Example of DMA Transfer Bus Timing

7.5.9

DMA Transfer (Dual Address Mode) Bus Cycles

Short Address Mode: Figure 7.18 shows a transfer example in which TEND output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
Rev. 2.00, 05/03, page 249 of 820