Host Interface Select Register (Hisel) - Renesas H8S/2100 Series Hardware Manual

20.3.19 Host Interface Select Register (HISEL)

HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt
request signal of each frame.
Initial
Bit Bit Name Value
7 SELSTR3 0
6 SELIRQ11 0
5 SELIRQ10 0
4 SELIRQ9 0
3 SELIRQ6 0
2 SELSMI 0
1 SELIRQ12 1
0 SELIRQ1 1
R/W
Slave Host Description

R/W Status Register 3 Selection
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. For
details of STR3, see section 20.3.12, Status
Registers 1 to 4 (STR1 to STR4).
0: Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 indicate processing status of
the LPC interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are readable/writable bits
which user can use as necessary

R/W Host IRQ Interrupt Select

R/W These bits select the state of the output on the
SERIRQ pins.

R/W
0: [When host interrupt request is cleared]

R/W
SERIRQ pin output is in the Hi-Z state

R/W
[When host interrupt request is set]

R/W
SERIRQ pin output is low

R/W
1: [When host interrupt request is cleared]
SERIRQ pin output is low
[When host interrupt request is set]
SERIRQ pin output is in the Hi-Z state.
Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 659 of 994
REJ09B0452-0100