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16.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. If receive data is sampled at the rising edge of the 8th pulse of the basic
clock, data is latched at the middle of each bit, as shown in figure 16.3. Thus the reception margin
in asynchronous mode is determined by formula (1) below.
1
D – 0.5
M = (0.5 –
}
) –
2N
M: Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16)} × 100
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 16.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00, 09/03, page 444 of 704
– (L – 0.5) F } × 100
N
[%] = 46.875 %
16 clocks
8 clocks
0
7
Start bit
... Formula (1)
[%]
15 0
D0
7
15 0
D1
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