Timing Of Cmfa And Cmfb Setting At Compare-Match; Timing Of Timer Output At Compare-Match; Figure 11.6 Timing Of Cmf Setting At Compare-Match; Figure 11.7 Timing Of Toggled Timer Output By Compare-Match A Signal - Renesas H8S/2437 Hardware Manual

11.5.2

Timing of CMFA and CMFB Setting at Compare-Match

The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
values match, the compare-match signal is not generated until the next TCNT input clock. Figure
11.6 shows the timing of CMF flag setting.
φ
TCNT
TCOR
Compare-match
signal
CMF

Figure 11.6 Timing of CMF Setting at Compare-Match

11.5.3

Timing of Timer Output at Compare-Match

When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 11.7 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
φ
Compare-match A
signal
Timer output pin

Figure 11.7 Timing of Toggled Timer Output by Compare-Match A Signal

N
N
N + 1
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