Timing Of Imfa To Imfd Flag Setting At Compare Match; Figure 12.21 Timing Of Imfa To Imfd Flag Setting At Compare Match - Renesas H8 Series Hardware Manual

12.5.6

Timing of IMFA to IMFD Flag Setting at Compare Match

If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
GRA to GRD
Compare
match signal
IMFA to IMFD
IRRTW

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match

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N
Section 12 Timer W
Rev. 3.00 Sep. 14, 2006 Page 185 of 408
REJ09B0105-0300