Timing Of Cmfa And Cmfb Setting When Compare-Match Occurs; Timing Of Timer Output When Compare-Match Occurs; Figure 12.4 Count Timing For External Clock Input; Figure 12.5 Timing Of Cmf Setting - Renesas H8S/2368 Series Hardware Manual

φ
External clock
input pin
Clock input
to TCNT
TCNT
12.5.2

Timing of CMFA and CMFB Setting when Compare-Match Occurs

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input.
Figure 12.5 shows this timing.
φ
TCNT
TCOR
Compare match
signal
CMF
12.5.3

Timing of Timer Output when Compare-Match Occurs

When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 12.6 shows the timing when the output is set to toggle at compare match A.
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Figure 12.4 Count Timing for External Clock Input

N
N

Figure 12.5 Timing of CMF Setting

N
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Rev. 2.00, 05/03, page 483 of 820
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