Figure 7.25 Example Of Transfer In Normal Transfer Mode By Cycle Stealing (Transfer Source Dsar = Odd Address And Source Address Increment); Figure 7.26 Example Of Transfer In Normal Transfer Mode By Cycle Stealing (Transfer Destination Ddar = Odd Address And Destination Address Decrement) - Renesas H8SX/1520 Series Hardware Manual

Section 7 DMA Controller (DMAC)
DMA byte
read cycle
Bφ
4m + 1
Address
bus
RD
LHWR
LLWR
TEND
Bus
released
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Source DSAR = Odd Address and Source Address Increment)
DMA word
read cycle
Bφ
4m
Address
bus
RD
LHWR
LLWR
TEND
Bus
released
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Destination DDAR = Odd Address and Destination Address Decrement)
Rev. 3.00 Mar. 14, 2006 Page 184 of 804
REJ09B0104-0300
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DMA word DMA byte DMA word
read cycle read cycle write cycle
4m + 2 4m + 4 4n
DMA word DMA byte DMA word
read cycle write cycle write cycle
4m + 2 4n + 5 4n + 6
DMA word DMA byte DMA word
write cycle read cycle read cycle
4n +2 4m + 5 4m + 6
Bus
released
DMA byte DMA word DMA word
write cycle read cycle read cycle
4n + 8 4m + 4 4m + 6
Bus
released
DMA byte DMA word DMA word
read cycle write cycle write cycle
4m + 8 4n + 4 4n + 6
Last transfer cycle
m and n are integers.
DMA byte DMA word DMA byte
write cycle write cycle write cycle
4n + 1 4n + 2 4n + 4
Last transfer cycle
m and n are integers.
Bus
released
Bus
released