Column Address Output Cycle Control; Row Address Output State Control; Figure 6.21 Example Of Access Timing With 3-State Column Address Output Cycle (Rast = 0) - Renesas H8S/2368 Series Hardware Manual

6.6.6

Column Address Output Cycle Control

The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.21
shows an example of the timing when a 3-state column address output cycle is selected.
Address bus
(
,
(
( )
Read
Data bus
(
Write
( )
Data bus
Note: n = 2, 3
Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle
6.6.7

Row Address Output State Control

If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the T
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
Rev. 2.00, 05/03, page 156 of 820
T
p
Row address
)
)
)
T T
r c1
High
High
(RAST = 0)
T T
c2 c3
Column address
r