Samsung S3C6400X User Manual page 1090

PCM AUDIO INTERFACE
PCM AUDIO INTERFACE
The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input
PCMCODEC_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a
serial shift clock, and a sync signal. Data is received from the external Codec over a serial input line. The serial
data in, serial data out, and sync signal are synchronized to the serial shift clock.
The serial shift clock, PCMSCLK, is generated from a programmable divide of the input PCMCODEC_CLK. The
sync signal PCMSYNC, is generated based upon a programmable number of serial clocks and is one serial clock
wide.
The PCM data words are 16-bits wide and serially shifted out 1-bit per PCMSCLK. Only one 16-bit word is
shifted out for each PCMSYNC. The PCMSCLK will continue to toggle even after all 16-bits have been shifted out.
The PCMSOUT data will be undefined after the 16-bit word is completed. The next PCMSYNC will signal the start
of the next PCM data word.
The TX FIFO provides the 16-bit data word to be serially shifted out. This data is serially shifted out MSB first,
one bit per PCMSCLK. The PCM serial output data PCMSOUT is clocked out using the rising edge of the
PCMSCLK. The MSB bit position relative to the PCMSYNC is programmable to be either coincident with the
PCMSYNC or one PCMCLK later. After all 16-bits have been shifted out, an interrupt can optionally be generated
indicating the end of the transfer.
When the data is being shifted out, the PCMSIN input is used to serially shift data in from the external codec.
The data is received MSB first and is clocked in the falling edge of PCMSCLK. The position of the first bit is
programmable to be coincident with the PCMSYNC or one PCMSCLK later.
The first 16-bits are serially shifted into the PCM_DATAIN register which is later loaded into the RX FIFO.
Subsequent bits are ignored until the next PCMSYNC.
Various Interrupts are available to indicate the status of the RX and TX FIFO. Each FIFO has a programmable
flag to indicate when the CPU needs to service the FIFO. For the RX FIFO there is an interrupt which will be
raised when the FIFO exceeds a certain programmable almost_full depth. Similarly there is a programmable
almost_empty interrupt for the TX FIFO.
PCM TIMING
The following figures show the timing relationship for the PCM transfers. Note in all cases, the PCM shift timing
is derived by dividing the input clock, PCMCODEC_CLK. While the timing is based upon the PCMCODEC_CLK,
there is no attempt to realign the rising edge of the output PCMSCLK with the original PCMCODEC_CLK input
clock. These edges will be skewed by internal delay through the pads as well as the divider logic. This does not
represent a problem because the actual shift clock, PCMSCLK, is output with the data. If the PCMSCLK output is
not used, the skew will be significantly less than the period of the PCMCODEC_CLK. It should not represent a
problem since most PCM interfaces capture data on the falling edge of the clock.
Figure 37-1 shows a PCM transfer with the MSB configured to be coincident with the PCMSYNC. This MSB
positioning corresponds to setting the MSB_POS_WR and MSB_POS_RD bits in PCMCTL register to be LOW.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
37-2
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR