Samsung S3C6400X User Manual page 1058

Watchdog Timer
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER OPERATION
Figure 34-1shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its
source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the
resulting frequency is divided again.
PCLK 8-bit Prescaler
WTCON[15:8]
The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON)
register. Valid prescaler values range from 0 to 2 8 -1. The frequency division factor can be selected as 16, 32, 64,
or 128.
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:
t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )
WTDAT & WTCNT
Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically
reloaded into the timer counter (WTCNT). For this reason, an initial value must be written to the watchdog timer
count (WTCNT) register, before the watchdog timer starts.
CONSIDERATION OF DEBUGGING ENVIRONMENT
When the S3C6400 is in debug mode using Embedded ICE, the watchdog timer must not operate.
The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal
(DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated
as the watchdog timer is expired.
34-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MUX
1/16
1/32
1/64
1/128
WTCON[4:3]
Figure 34-1 Watchdog Timer Block Diagram
S3C6400 RISC MICROPROCESSOR
WTDAT
Interrupt
WTCNT
Reset Signal Generator
(Down Counter)
WTCON[2]
RESET
WTCON[0]