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AC97 CONTROLLER
Codec ready interrupt enable
PCM out channel underrun
interrupt enable
PCM in channel overrun
interrupt enable
Mic in channel overrun
interrupt enable
PCM out channel threshold
interrupt enable
PCM in channel threshold
interrupt enable
MIC in channel threshold
interrupt enable
-
PCM out channel transfer
mode
PCM in channel transfer
mode
MIC in channel transfer mode
-
Transfer data enable using
AC-link
AC-Link on
Warm reset
Cold reset
AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT)
This is the status register. When the interrupt is occurs, you can check what the interrupt source is.
Register
AC_GLBSTAT
AC_GLBSTAT
-
Codec ready interrupt
PCM out channel underrun
interrupt
PCM in channel overrun
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
35-12
Specifications and information herein are subject to change without notice.
[22]
0 : Disable
[21]
0 : Disable
1 : Enable ( FIFO is empty)
[20]
0 : Disable
1 : Enable ( FIFO is full)
[19]
0 : Disable
1 : Enable ( FIFO is full)
[18]
0 : Disable
1 : Enable ( FIFO is half empty)
[17]
0 : Disable
1 : Enable ( FIFO is half full)
[16]
0 : Disable
1 : Enable ( FIFO is half full)
[15:14]
Reserved.
[13:12]
00 : Off
[11:10]
00 : Off
[9:8]
00 : Off
[7:4]
Reserved.
[3]
0 : Disable
[2]
0 : Off
1 : SYNC signal transfer to Codec
[1]
0 : Normal
1 : Wake up codec from power down
[0]
0 : Normal
1 : Reset Codec and Controller logic
Address
R/W
0x7F001004
R
Bit
[31:23]
Reserved.
[22]
0 : Not requested
[21]
0 : Not requested
[20]
0 : Not requested
1 : Enable
01 : PIO
10 : DMA
01 : PIO
10 : DMA
01 : PIO
10 : DMA
1 : Enable
Description
AC97 Global Status Register
Description
1 : Requested
1 : Requested
1 : Requested
S3C6400 RISC MICROPROCESSOR
11 : Reserved
11 : Reserved
11 : Reserved
Reset Value
0x00000001
Initial State
0
0
0
0
0
0
0
00
00
00
00
0000
0
0
0
0
0x00
0
0
0
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