Samsung S3C6400X User Manual page 1081

IIS-BUS INTERFACE
SAMPLING FREQUENCY AND MASTER CLOCK
Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 36-1. Because RCLK
is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) must be
determined properly.
Table 36-1. CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs)
IISLRCK 8.000
(fs) kHz
2.0480
CODECLK 3.0720
(MHz)
4.0960
6.1440
IIS CLOCK MAPPING TABLE
On selecting BFS, RFS, and BLC bits of I2SMOD register, you must refer to the following table. Table 36-2 shows
the allowable clock frequency mapping relations.
Clock Frequency
BFS 16 fs (10B)
24 fs (11B)
32 fs (00B)
48 fs (01B)
Descriptions
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
36-6
Specifications and information herein are subject to change without notice.
11.025 16.000 22.050
kHz kHz kHz
2.8224 4.0960 5.6448
4.2336 6.1440 8.4672
5.6448 8.1920 11.2900
8.4672 12.2880 16.9340
Table 36-2 IIS clock mapping table
256 fs (00B)
(a)
-
(a) (b)
-
(a) Allowed when BLC is 8-bit
(b) Allowed when BLC is 16-bit
32.000 44.100 48.000
kHz kHz kHz
256fs
8.1920 11.2896 12.2880
384fs
12.2880 16.9344 18.4320
512fs
16.3840 22.5790 24.5760
768fs
24.5760 33.8690 36.8640
RFS
512 fs (01B) 384 fs (10B)
(a)
-
(a) (b)
-
S3C6400X RISC MICROPROCESSOR
64.000 88.200
kHz kHz
16.3840 22.5792
24.5760 33.8688
32.7680 45.1580
49.1520 67.7380
768 fs (11B)
(a)
(a)
(a) (b) (a) (b)
(a) (b) (a) (b)
96.000
kHz
24.5760
36.8640
49.1520
73.7280
(a)
(a)