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S3C6400X RISC MICROPROCESSOR
Register
PCM_CLKCTL
0x7F009004
0x7F00A004
The bit definitions for the PCM_CTL Control Register are described below:
PCM_CLKCTL
Reserved
CTL_SERCLK_EN
CTL_SERCLK_SEL
SCLK_DIV
SYNC_DIV
Address
R/W
R/W
Bit
[31:20]
Reserved
[19]
Enable the serial clock division logic.
Must be HIGH for the PCM to operate
(if it is high, SCLK and FSYNC is operated.)
[18]
Select the source of the serial clock
0 – external_codec_clock input
1 - PCLK
[17:9]
Controls the divider used to create the PCMSCLK based on
the PCMCODEC_CLK
Final clock will be source_clk / 2*(sclk_div+1)
[8:0]
Controls the frequency of the PCMSYNC signal based on the
PCMSCLK.
Freq. of PCMSYNC = Freq. of PCMSCLK/(SYNC_DIV+1)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Control the PCM Audio Inteface
Description
PCM AUDIO INTERFACE
Reset Value
0x00000000
Initial
State
0
0
000
000
37-9
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