Samsung S3C6400X User Manual page 1069

S3C6400 RISC MICROPROCESSOR
AC97 POWER-DOWN
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
Powering Down the AC-link
The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set
to 1 (by writing 0x1000). Then the Primary Codec drives both BITCLK and SDATA_IN to a logic low voltage level.
The sequence follows the timing diagram as shown in Figure 35-7.
The AC97 Controller transmits the write to Power-down register (0x26) over the AC-link. Set up the AC97
Controller so that it does not transmit data to slots 3-12 when it writes to the Power-down register bit PR4 (data
0x1000), and it does not require the Codec to process other data when it receives a power down request. When
the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level. The AC97
Controller drives SYNC and SDATA_OUT to a logic low level after programming the AC_GLBCTRL register.
Waking up the AC-link - Wake Up Triggered by the AC97 Controller
AC-link protocol provides a cold AC97 reset and a warm AC97 reset. The current power-down state ultimately
dictates which AC97 reset is used. Registers must stay in the same state during all power-down modes unless a
cold AC97 reset is performed. In a cold AC97 reset, the AC97 registers are initialized to their default values. After
a power down, the AC-link must wait for a minimum of four audio frame times after the frame in which the power
down occurred before it can be reactivated by reasserting the SYNC signal. When AC-link powers up, it indicates
readiness through the Codec ready bit (input slot 0, bit 15).
slot 12
prev.frame
slot 12
prev.frame
Figure 35-7. AC97 Power-down Timing
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Write to Data
TAG
0X26 PR4
TAG
AC97 CONTROLLER
35-9