Table of Contents
Advertisement
S3C6400X RISC MICROPROCESSOR
Name
Xi2sLRCK[1]
Xi2sDI[1]
Xi2sDO[1]
FUNCTIONAL DESCRIPTIONS
IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in Figure 36-1. Note that each FIFO has 32-bit width and 16 depth structure, which
contains left/right channel data. Therefore FIFO access and data transfer are handled with left/right pair unit.
Figure 36-1 shows the functional block diagram of IIS interface.
MASTER/SLAVE MODE
Master or slave mode can be selected by setting IMS bit of IISMOD register. In master mode, I2SSCLK and
I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for
generating I2SSCLK and I2SLRCLK by dividing. The IIS pre-scaler (clock divider) is employed for generating a
root clock with divided frequency from internal system clock. In external master mode, the root clock can be fed
from IIS external directly. The I2SSCLK and I2SLRCLK are supplied from the pin (GPIOs) in slave mode.
Master/Slave mode is different with TX/RX. Master/Slave mode presents the direction of I2SLRCLK and
I2SSCLK. Direction of I2SCDCLK (This is only auxiliary.) is not important. If IIS bus interface transmits clock
signals to IIS codec, IIS bus is in master mode. But if IIS bus interface receives clock signal from IIS codec, IIS
bus is in slave mode. TX/RX mode indicates the direction of data flow. If IIS bus interface transmits data to IIS
codec, this is TX mode. Conversely, IIS bus interface receives data from IIS codec that is RX mode. Let's
distinguish Master/Slave mode from TX/RX mode.
Figure 36-2 shows the route of the root clock with internal master or external master mode setting in IIS clock
control block and system controller. Note that RCLK indicates root clock and this clock can be supplied to external
IIS codec chip at internal master mode.
Type
Source/Destination
Input/Output
Input
Output
Figure 36-2. IIS Clock Control Block Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Pad
IIS-bus1 channel select clock
Pad
IIS-bus1 serial data input
Pad
IIS-bus1 serial data output
IIS-BUS INTERFACE
Description
36-3
Advertisement
Table of Contents
