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S3C6400X RISC MICROPROCESSOR
LRP
SDF
RFS
BFS
BLC
IISFIC
Register
IISFIC
01: Receive only mode
10: Transmit and receive simultaneous mode
11: Reserved
[7]
R/W
Left/Right channel clock polarity select.
0: Low for left channel and high for right channel
1: High for left channel and low for right channel
[6:5]
R/W
Serial data format.
00: IIS format
01: MSB-justified (left-justified) format
10: LSB-justified (right-justified) format
11: Reserved
[4:3]
R/W
IIS root clock (codec clock) frequency select.
00: 256 fs, where fs is sampling frequency
01: 512 fs
10: 384 fs
11: 768 fs
[2:1]
R/W
Bit clock frequency select.
00: 32 fs, where fs is sampling frequency
01: 48 fs
10:16 fs
11: 24 fs
[0]
R/W
Bit length per channel.
0: 16-bit, 1: 8-bit
Address
0x7F002008
0x7F003008
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIS interface FIFO control register
IIS-BUS INTERFACE
Reset Value
0x0000_0000
36-11
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