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IIS-BUS INTERFACE
IISFIC
[31:16]
TFLUSH
[14:13]
FTXCNT
[12:8]
RFLUSH
FRXCNT
IISPSR
Register
IISPSR
IISPSR
[31:16]
PSRAEN
PSVALA
[13:8]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
36-12
Specifications and information herein are subject to change without notice.
Bit
R/W
Reserved. Program to zero.
R/W
[15]
R/W
TX FIFO flush command.
0: No flush, 1: Flush
R/W
Reserved. Program to zero.
R
TX FIFO data count. FIFO has 16 dept, so value ranges from 0 to
16.
N: Data count N of FIFO
[7]
R/W
RX FIFO flush command.
0: No flush, 1: Flush
[6:5]
R/W
Reserved. Program to zero.
[4:0]
R
RX FIFO data count. FIFO has 16 dept, so value ranges from 0 to
16.
N: Data count N of FIFO
Address
0x7F00200C
IIS interface clock divider control register
0x7F00300C
Bit
R/W
Reserved. Program to zero.
R/W
[15]
R/W
Pre-scaler (Clock divider) A active.
0: Inactive, 1: Active
[14]
R/W
Reserved. Program to zero.
R/W
Pre-scaler (Clock divider) A division value.
N: Division factor is N+1
[7:0]
R/W
Reserved. Program to zero.
S3C6400X RISC MICROPROCESSOR
Description
Description
Description
Reset Value
0x0000_0000
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