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IIS-BUS INTERFACE
DMA Transfer
In the DMA transfer mode, the transmitter or receiver FIFO are accessible by DMA controller. DMA service
request is activated internally by the transmitter or receiver FIFO state. The FTXEMPT, FRXEMPT, FTXFULL,
and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state. Especially,
FTXEMPT and FRXFULL bit are the ready flag for DMA service request; the transmit DMA service request is
activated when TXFIFO is not empty and the receiver DMA service request is activated when RXFIFO is not full.
The DMA transfer uses only handshaking method for single data. Note that during DMA acknowledge activation;
the data read or write operation must be performed.
* Reference : DMA request point
- TX mode : ( FIFO is not full ) & ( TXDMACTIVE is active )
- RX mode : ( FIFO is not empty ) & ( RXDMACTIVE is active )
AUDIO SERIAL DATA FORMAT
IIS-BUS FORMAT
The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select
clock I2SLRCLK, and serial bit clock I2SBCLK; the device generating I2SLRCLK and I2SBCLK is the master.
Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the
LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period after the
I2SLRCLK is changed. Serial data sent by the transmitter may be synchronized with either the trailing or the
leading edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of
the serial clock signal. Therefore transmitting data that is synchronized with the leading edge has some
restrictions.
The LR channel select line indicates the channel being transmitted. I2SLRCLK may be changed either on a
trailing or leading edge of the serial clock, but it is not mandatory to be symmetrical. In the slave, this signal is
latched on the leading edge of the clock signal. The I2SLRCLK line changes one clock period before the MSB is
transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for
transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word.
MSB (LEFT) JUSTIFIED
MSB-Justified (Left-Justified) format is similar to IIS bus format, except that in MSB-justified format, the transmitter
always sends the MSB of the next word at the same time whenever the I2SLRCLK is changed.
LSB (RIGHT) JUSTIFIED
LSB-Justified (Right-Justified) format is opposite to the MSB-justified format. In other word, the transferring serial
data is aligned with ending point of I2SLRCLK transition.
Figure 36-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
36-4
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR
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