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IIS-BUS INTERFACE
TXDMACTIVE
RXDMACTIVE
I2SACTIVE
IISMOD
Register
IISMOD
IISMOD
[31:13]
CDCLKCON
IMS
[11:10]
TXR
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
36-10
Specifications and information herein are subject to change without notice.
[2]
R/W
Tx DMA active (start DMA request). Note that when this bit is set
from high to low, the DMA operation will be forced to stop
immediately.
0: Inactive, 1: Active
[1]
R/W
Rx DMA active (start DMA request). Note that when this bit is set
from high to low, the DMA operation will be forced to stop
immediately.
0: Inactive, 1: Active
[0]
R/W
IIS interface active (start operation).
0: Inactive, 1:Active
Address
0x7F002004
0x7F003004
Bit
R/W
Reserved. Program to zero.
R/W
[12]
R/W
Determine codec clock source
0 : Use internal codec clock source
1 : Get codec clock source from external codec chip
(For more information refer to Figure 36-2)
R/W
IIS master (internal/external) or slave mode select.
00: Master mode (divide mode, using PCLK)
01: Master mode (bypass mode, using I2SCLK)
10: Slave mode (divide mode, using PCLK)
11: Slave mode (bypass mode, using I2SCLK)
(For more information refer to Figure 36-2)
[9:8]
R/W
Transmit or receive mode select.
00: Transmit only mode
Description
IIS interface mode register
Description
S3C6400X RISC MICROPROCESSOR
Reset Value
0x0000_0000
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