Samsung S3C6400X User Manual page 1080

S3C6400X RISC MICROPROCESSOR
length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SBCLK (BFS is 48 fs, where fs is sampling
frequency; I2SLRCLK frequency).
LRCLK
BCLK
SD
LRCLK
BCLK
MSB
SD
(1st)
LRCLK
BCLK
SD
LEFT
MSB 2nd
N-1th
(1st) Bit
Bit
LEFT
2nd N-1th
Bit Bit
MSB - Justified
LEFT
1st N-2th
Bit Bit
LSB - Justified
Figure 36-3. IIS Audio Serial Data Formats
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MSB 2nd
(1st) Bit
I 2 S Format ( N = 8 or 16 )
MSB 2nd
(1st) Bit
( Left - Justified ) Format ( N = 8 or 16 )
LSB 1st
(N-1th) Bit
( Right - Justified ) Format ( N = 8 or 16 )
IIS-BUS INTERFACE
RIGHT
N-1th
Bit
RIGHT
N-1th
Bit
RIGHT
N-2th LSB
Bit (N-1th)
36-5