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S3C6400X RISC MICROPROCESSOR
input
PCMCODEC_CLK
output
PCMSCLK
output
PCMSYNC
output
PCMSOUT
PCMSIN
input
internal
pcm_irq
(sync to DSP clk)
Figure 37-2 shows a PCM transfer with the MSB configured one shift clock after the PCMSYNC. This MSB
positioning corresponds to setting the MSB_POS_WR and MSB_POS_RD bits in PCMCTL register to be HIGH.
input
PCMCODEC_CLK
output
PCMSCLK
output
PCMSYNC
output
PCMSOUT
PCMSIN
input
internal
pcm_irq
(sync to DSP clk)
15
15
Figure 37-1 PCM timing, POS_MSB_WR/RD = 0
Figure 37-2 PCM timing, POS_MSB_WR/RD = 1
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
. . .
14
13
1
0
. . .
14
13
1
0
. . .
15
14
1
0
. . .
15
14
1
0
PCM AUDIO INTERFACE
dont care
15
14
dont care
15
14
datain_reg_valid
dont care
15
dont care
15
datain_reg_valid
37-3
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