Samsung S3C6400X User Manual page 1082

S3C6400X RISC MICROPROCESSOR
PROGRAMMING GUIDE
The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA
controller.
INITIALIZATION
1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode and check signal's direction.
I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type. The each of I2SSDI and I2SSDO is a input and output.
2. You must select a clock source. S3C6400 has three clock sources. Those are PCLK, EPLL and external
codec. For more information please refer to figure 36-2.
PLAY MODE (TX MODE) WITH DMA
1. TXFIFO is flushed before operation. If you don't distinguish Master/Slave mode from TX/RX mode, you must
study Master/Slave mode and TX/RX mode. For more information please refer to Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register) correctly.
3. To operate system in stability, the internal TXFIFO must be nearly full before transmission. DMA starts
because of this reason.
4. IIS bus doesn't support the interrupt. You can only check the state by polling through accessing SFR.
5. If TXFIFO is full, you make I2SACTIVE be asserted.
RECORDING MODE (RX MODE) WITH DMA
1. RXFIFO is flushed before operation. If you don't distinguish between Master/Slave mode and TX/RX mode,
you must study Master/Slave mode and TX/RX mode. For more information please refer to Master/Slave chapter.
2. Configure I2SMOD register and I2SPSR (IIS pre-scaler register) correctly.
3. To operate system in stability, the internal RXFIFO must have at least one data before DMA operation.
Because of this reason, you make I2SACTIVE be asserted.
4. Check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, start the RXDMACTIVE.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IIS-BUS INTERFACE
36-7