Samsung S3C6400X User Manual page 1073

S3C6400 RISC MICROPROCESSOR
interrupt
MIC in channel overrun interrupt
PCM out channel threshold
interrupt
PCM in channel threshold
interrupt
MIC in channel threshold
interrupt
-
Controller main state
AC97 CODEC COMMAND REGISTER (AC_CODEC_CMD)
When you control writing or reading, you must set the Read enable bit. If you want to write data to the AC97
Codec, you set the index (or address) of the AC97 Codec and data.
Register
AC_CODEC_CMD
AC_CODEC_CMD
-
Read enable
Address
Data
Note:
When the commands are written on the AC_CODDEC_CMD register, It is recommended to have the delay time
between the command and the next command is more than 1 / 48KHz.
AC97 CODEC STATUS REGISTER (AC_CODEC_STAT)
If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid.
Register
AC_CODEC_STAT
AC_CODEC_STAT
-
Address
[19]
0 : Not requested
[18]
0 : Not requested
[17]
0 : Not requested
[16]
0 : Not requested
[15:3]
Reserved.
000 : Idle
[2:0]
011 : Active
Address R/W
0x7F001008 R/W
Bit
[31:24] Reserved
[23] 0 : Command write
[22:16] Codec command address
[15:0] Codec command data
Address R/W
0x7F00100C R
Bit
[31:23] Reserved.
[22:16] Codec status address
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 : Requested
1 : Requested
1 : Requested
1 : Requested
001 : Init 010 : Ready
100 : LP 101 : Warm
Description
AC97 Codec Command Register
Description
1 : Status read
(1)
Description
AC97 Codec Status Register
Description
AC97 CONTROLLER
0
0
0
0
0x000
001
Reset Value
0x00000000
Initial State
0x00
0
0x00
0x0000
Reset Value
0x00000000
Initial State
0x00
0x00
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