Samsung S3C2501X User Manual

32-bit risc microprocessor

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查询S3C2501X供应商

捷多邦，专业PCB打样工厂，24小时加急出货

S3C2501X

32-BIT RISC

MICROPROCESSOR

USER'S MANUAL

Revision 1

Table of Contents

Summary of Contents for Samsung S3C2501X

Page 1 查询S3C2501X供应商捷多邦，专业PCB打样工厂，24小时加急出货 S3C2501X 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1...
Page 2: Important Notice
Samsung products are not designed, intended, or use of the information contained herein. authorized for use as components in systems Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 3: Table Of Contents
2.12 Reset ...............................2-16 2.13 Introduction for ARM940T ........................2-17 2.14 ARM940T Block Diagram.........................2-18 2.15 About The ARM940T Programmer's Model ..................2-19 2.15.1 Data Abort Model........................2-20 2.15.2 Instruction Set Extension Spaces..................2-20 2.16 ARM940T CP15 Registers .......................2-21 2.16.1 CP15 Register Map Summary ....................2-21 S3C2501X...
Page 4 3.9.2 Shifted Register Offset......................3-29 3.9.3 Bytes and Words ........................3-29 3.9.4 Use of R15..........................3-31 3.9.5 Restriction on the Use of Base Register ................. 3-31 3.9.6 Data Aborts..........................3-31 3.9.7 Instruction Cycle Times......................3-31 3.9.8 Assembler Syntax........................3-32 S3C2501X...
Page 5 3.14.3 Instruction Cycle Times ......................3-52 3.14.4 Assembler Syntax.........................3-52 3.15 Coprocessor Data Transfers (LDC, STC) ..................3-53 3.15.1 The Coprocessor Fields ......................3-53 3.15.2 Addressing Modes ........................3-54 3.15.3 Address Alignment........................3-54 3.15.4 Use of R15 ...........................3-54 3.15.5 Data Aborts...........................3-54 3.15.6 Instruction Cycle Times ......................3-54 3.15.7 Assembler Syntax.........................3-55 S3C2501X...
Page 6 3.25.1 Operation..........................3-76 3.25.2 Instruction Cycle Times......................3-76 3.26 Format 7: Load/Store With Register Offset..................3-77 3.26.1 Operation..........................3-77 3.26.2 Instruction Cycle Times......................3-78 3.27 Format 8: Load/Store Sign-Extended Byte/Half-Word ..............3-79 3.27.1 Operation..........................3-79 3.27.2 Instruction Cycle Times......................3-80 S3C2501X...
Page 7 3.38 Format 19: Long Branch With Link....................3-95 3.38.1 Operation..........................3-95 3.38.2 Instruction Cycle Times ......................3-96 3.39 Instruction Set Examples .........................3-97 3.39.1 Multiplication by a Constant Using Shifts and Adds...............3-97 3.39.2 General Purpose Signed Divide....................3-98 3.39.3 Division by a Constant ......................3-100 S3C2501X...
Page 8 5.7.3 Address Mapping ........................5-42 5.7.4 SDRAM Commands....................... 5-44 5.7.5 External Data Bus Width......................5-45 5.7.6 Merging Write Buffer ......................5-45 5.7.7 Self Refresh........................... 5-45 5.7.8 Basic Operation ........................5-46 5.7.9 SDRAM Special Registers ..................... 5-47 5.7.10 SDRAM Controller Timing....................5-54 viii S3C2501X...
Page 9 7.4.1 BDMA Relative Special Register ....................7-15 7.4.2 MAC Relative Special Register....................7-24 7.5 Ethernet Operations...........................7-37 7.5.1 MAC Frame Format........................7-37 7.5.2 The MII Station Manager ......................7-45 7.5.3 Full-Duplex Pause Operations ....................7-46 7.5.4 Error Signalling........................7-48 7.5.5 Timing Parameters for MII Transactions .................7-50 S3C2501X...
Page 10 9.6 GDMA Transfer Timing Data......................9-19 9.6.1 Single and One Data Burst Mode ..................9-20 9.6.2 Single and Four Data Burst Mode ..................9-21 9.6.3 Block and One Data Burst Mode .................... 9-22 9.6.4 Block and Four Data Burst ..................... 9-23 S3C2501X...
Page 11 12.3.2 I/O Port Function Control Register ..................12-4 12.3.3 I/O Port Control Register for GDMA..................12-7 12.3.4 I/O Port Control Register for External Interrupt ..............12-8 12.3.5 I/O Port External Interrupt Clear Register................12-10 12.3.6 I/O Port Data Register ......................12-11 12.3.7 I/O Port Drive Control Register .....................12-11 S3C2501X...
Page 12 14.6.5 Watchdog Timer Register ....................14-9 Chapter 15Electrical Data 15.1 Overview ............................15-1 15.2 Absolute Maximum Ratings......................15-1 15.3 Recommended Operating Conditions....................15-1 15.4 DC Electrical Specifications ......................15-2 15.5 AC Electrical Characteristics ......................15-4 Chapter 16Mechanical Data 16.1 Overview ............................16-1 S3C2501X...
Page 13 Title Page Number Number S3C2501X Block Diagram ..................1-4 S3C2501X Pin Assignment Diagram ..............1-5 Big-Endian Addresses of Bytes within Words............2-2 Little-Endian Addresses of Bytes Words ..............2-2 Register Organization in ARM State ...............2-5 Register Organization in THUMB State ..............2-6 Mapping of THUMB State Registers onto ARM State Registers......2-7 Program Status Register Format ................2-8...
Page 14 External Address Bus Diagram ................4-4 Priority Groups of S3C2501X................. 4-5 AHB Programmable Priority Registers ..............4-6 Shows the Clock Generation Logic of the S3C2501X..........4-14 Divided System Clock Timing Diagram..............4-19 Memory Bank Address map................... 5-4 Memory Controller Bus Signals................5-6 8-bit ROM, SRAM and Flash Basic Connection .............
Page 15 CSMA/CD Receive Operation ................7-44 7-12 MAC Control Frame Format ...................7-46 7-13 Timing Relationship of Transmission Signals at MII..........7-50 7-14 Timing Relationship of Reception Signals at MII.............7-50 7-15 MDIO Sourced by PHY...................7-50 7-16 MDIO Sourced by STA ...................7-50 DES/3DES Block Diagram ..................8-2 S3C2501X...
Page 16 11-6 High-Speed UART Receive Buffer Register............11-17 11-7 High-Speed UART Baud Rate Divisor Register............11-18 11-8 High-Speed UART Baud Rate Generator (BRG)............ 11-19 11-9 High-Speed UART Control Character 1 Register............ 11-20 11-10 High-Speed UART Control Character 2 Register............ 11-21 S3C2501X...
Page 17 Interrupt Priority Register..................13-8 14-1 Timer Output Signal Timing..................14-2 14-2 32-Bit Timer Block Diagram ...................14-3 14-3 Timer Mode Register....................14-5 14-4 Timer Data Registers....................14-6 14-5 Timer Count Registers....................14-7 14-6 Timer Interrupt Clear Register ................14-8 14-7 Watchdog Timer Register..................14-9 16-1 272-BGA-2727-AN Package Dimensions..............16-2 S3C2501X xvii...
Page 19: List Of Tables
List of Tables Table Title Page Number Number S3C2501X Signal Descriptions ................1-12 S3C2501X Pad Type and Feature ................1-26 S3C2501X System Configuration ................1-27 S3C2501X Memory Controller ................1-27 S3C2501X SDRAM Controller ................1-27 S3C2501X IIC Controller ..................1-28 S3C2501X Ethernet Controller 0................1-28 S3C2501X Ethernet Controller 1................1-29 S3C2501X DES Controller..................1-30...
Page 20 The Base Address of Remapped Memory.............. 4-3 AHB Bus Priorities for Arbitration................4-4 Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins ..4-9 P, M, S values of the S3C2501X PLL ..............4-13 System Configuration Registers................4-15 S3C2501X...
Page 21 5-25 SDRAM Configuration Register ................5-47 5-26 SDRAM Command Register...................5-50 5-27 SDRAM Refresh Timer Register................5-52 5-28 SDRAM Write Buffer Time-out Register ..............5-53 Control Status Register...................6-8 IICCON Register Description ..................6-8 IICBUF Register .....................6-10 IICPS Register .......................6-10 IICCNT Register .....................6-11 IICPND Register.....................6-11 S3C2501X...
Page 22 7-24 CAMEN Register ....................7-33 7-25 MISSCNT Register ....................7-34 7-26 PZCNT Register ....................7-35 7-27 RMPZCNT Register....................7-35 7-28 CAM Register ......................7-36 7-29 MAC Frame Format Description ................7-37 7-30 STA Frame Structure Description ................7-45 xxii S3C2501X...
Page 23: Overview
DES/3DES Input Data FIFO Description..............8-8 8-15 DES/3DES Output Data FIFO Description ..............8-8 GDMA Special Registers Overview ................9-3 GDMA Programmable Priority Registers ..............9-4 DCON0/1/2/3/4/5 Registers ..................9-9 GDMA Control Register Description ...............9-9 DSAR0/1/2/3/4/5 and DDAR0/1/2/3/4/5 Registers...........9-12 DTCR0/1/2/3/4/5 Registers..................9-13 DRER0/1/2/3/4/5 Registers..................9-14 DIPR0/1/2/3 Registers ....................9-15 S3C2501X xxiii...
Page 24 I/O Port Special Registers ..................12-2 12-2 IOPMODE1/2 Registers..................12-2 12-3 IOPCON1/2 Register ..................... 12-4 12-4 IOPGDMA Register ....................12-7 12-5 IOPEXTINT Register ..................... 12-8 12-6 IOPEXTINTPND Register ..................12-10 12-7 IOPDATA1/2 Register.................... 12-11 12-8 IOPDRV1/2 Register....................12-11 xxiv S3C2501X...
Page 25 List of Tables (Concluded) Table Title Page Number Number 13-1 S3C2501X Internal Interrupt Sources..............13-2 13-2 S3C2501X External Interrupt Sources ..............13-3 13-3 INTMOD, EXTMOD Register..................13-3 13-4 INTMASK, EXTMASK Register ................13-5 13-5 Interrupt Priority Register..................13-8 13-6 INTOFFSET_FIQ, INTOFFSET_IRQ Register ............13-9 13-7 Index Value of Interrupt Sources ................13-10 13-8 IPRIORHI, IPRIORLO Register ................13-12...
Page 26: Product Overview
This highly integrated microcontroller enables customers to save system costs and increase performance over other 32-bit microcontroller. The S3C2501X is built based on an outstanding CPU core: The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-on-a-chip processor solutions.
Page 27: Features
PRODUCT OVERVIEW S3C2501X 1.2 FEATURES ARM940T Core processor On-chip CAM (21 addresses) • • Fully 16/32-bit RISC architecture. Full-duplex mode for doubled bandwidth • • Harvard cache architecture with separate 4KB Pause operation hardware support for full- Instruction and Data cache duplex flow control •...
Page 28 S3C2501X PRODUCT OVERVIEW 1.2 FEATURES (Continue) General DMA Channels C Controller • • Six GDMA channels Master mode operation only • • Memory to memory data transfer Baud rate generator for serial clock • Memory to peripheral data transfer (high-speed...
Page 29: Block Diagram
Bridge GPIOs DES/3DES Sys. Bus Arbiter 2-bank SDRAM Memory Controller GDMA 8-bank Flash/ROM/ SRAM/Ext Timers REQ/ACK External Clock Gen. Bus Master & Reset Drv. with 4 PLLs 20 MHz or 10 MHz 25 MHz OSC. Figure 1-1. S3C2501X Block Diagram...
Page 30: Package Diagram
S3C2501X PRODUCT OVERVIEW 1.4 PACKAGE DIAGRAM TOP View A1 ball pad corner Figure 1-2. S3C2501X Pin Assignment Diagram...
Page 31: Pin Assignment
PRODUCT OVERVIEW S3C2501X 1.5 PIN ASSIGNMENT Pin # Pin Name Direction Pin # Pin Name Direction ADDR17 PHY_FREQ ADDR15 GPIO59 ADDR11 GPIO56 ADDR8 GPIO52 ADDR5 GPIO49 ADDR1 GPIO47 XDATA27 GPIO44 XDATA26 XDATA23 ADDR20 XDATA21 ADDR19 TXD0_0/TXD_10M ADDR16 MDC_0 ADDR12 PHY_CLKO...
Page 32 S3C2501X PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction TXD0_1/LOOP10M XDATA13 MDIO_0 XDATA10 COL_0 RXD0_0/RXD_10M RX_CLK_0 GPIO60 TX_ERR_0/PCOMP_10M VDD1.8 VDD1.8 GPIO53 VDD3.3 XDATA12 GPIO43 XDATA9 ADDR23/ALE XDATA7 VDD1.8 RXD0_2 ADDR13 RXD0_1 VDD3.3...
Page 33 PRODUCT OVERVIEW S3C2501X 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction VDD1.8_A VDD1.8_A VDD1.8 CPU_FILTER GND_A XDATA1 VDD3.3 XDATA0 nWBE1/nBE1/DQM1 nSDCAS nWBE0/nBE0/DQM0 nSDRAS nWBE2/nBE2/DQM2 GND_A VDD1.8_A VDD1.8 VDD1.8 BUS_FILTER PHY_FILTER VDD1.8 GND_A nSDCS1 nRCS5...
Page 34 S3C2501X PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction VDD1.8_A TX_ERR_1/PCOMP_10M VDD1.8 RXD1_0/RXD_10M BUS_FREQ2 CPU_FREQ2 XBMREQ nRCS2 XBMACK nRCS3 TX_EN_1 nRCS4 CRS_1 GND_A RXD1_1 MDC_1 COL_1 TXD1_1/LOOP_10M VDD3.3 B0SIZE1 HURXD/GPIO35 nRCS0 GPIO0 nRCS1 VDD3.3...
Page 35 PRODUCT OVERVIEW S3C2501X 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction RX_CLK_1 RXD1_3 RXD1_2 RX_ERR_1 RX_DV_1/LINK10M CUTXD GPIO29 GPIO28 UCLK GPIO32 GPIO34 XCLK HUnDTR/GPIO37 HUnDSR/GPIO38 HUnCTS/GPIO40 HUnDCD/GPIO41 GPIO1 GPIO2 GPIO5 GPIO4 xINT1/GPIO9 xINT0/GPIO8 xINT5/GPIO13...
Page 36 S3C2501X PRODUCT OVERVIEW 1.5 PIN ASSIGNMENT (Continue) Pin # Pin Name Direction Pin # Pin Name Direction CURXD GPIO7 CLKSEL xINT3/GPIO11 GPIO30 xGDMA_Req1/GPIO15 GPIO31 xGDMA_Ack0/GPIO18 GPIO33 xGDMA_Ack2/GPIO20 HUTXD/GPIO36 TIMER1/GPIO23 HUnRTS/GPIO39 HCLKO GPIO3 GPIO6 nTRST 1-11...
Page 37: Signal Description
Pin Name Type Pad Type Description System XCLK Phic S3C2501X PLL Clock Source. If CLKSEL is Config Low, PLL output clock is used as the system (20) clock. If CLKSEL is high, XCLK is used as the system clock. HCLKO phbst24 System clock output.
Page 38 0 = normal operating mode 1 = chip test mode. phicd BIG endian mode select pin When this pin is set to “0”, the S3C2501X operates in litte endian mode. When this pin is set to “1”, the S3C2501X operates in big endian mode.
Page 39 ADDR[10]/AP. XDATA[31:0] phbsut20 External bi-directional 32bit data bus. The S3C2501X supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank. nSDCS[1:0] phot20 Not chip select strobe for SDRAM.
Page 40 Not ROM/SRAM/Flash/ External I/O Chip select. The S3C2501X supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks. B0SIZE[1:0] phic Bank 0 Data Bus Access Size.
Page 41 SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2501X can get the control of the bus and the XBMACK goes “low”. XBMACK phob8 External bus Acknowledge.
Page 42 S3C2501X PRODUCT OVERVIEW Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet MDC_0 phob12 Management Data Clock. Controller0 The signal level at the MDC pin is used as a (18) timing reference for data transfers that are controlled by the MDIO signal.
Page 43 PRODUCT OVERVIEW S3C2501X Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TX_EN_0 phob4 Transmit Enable/Transmit Enable for 10M. Controller0 TX_EN provides precise framing for the data (18) carried on TXD[3:0]. This pin is active during...
Page 44 S3C2501X PRODUCT OVERVIEW Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet CRS_0 phis Carrier Sense/Carrier Sense for 10M. Controller0 CRS is asserted asynchronously with (18) minimum delay from the detection of a non- idle medium in MII mode. CRS_10M is asserted when a 10-Mbit/s PHY has data to transfer.
Page 45 PRODUCT OVERVIEW S3C2501X Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet RX_ERR_0 phisd Receive Error. Controller0 PHY asserts RX_ERR synchronously (18) whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV.
Page 46 S3C2501X PRODUCT OVERVIEW Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TXD1[3:0]/ phob12 Transmit Data/Transmit Data for 10M. Controller1 TXD_10M/ Transmit data is aligned on nibble boundaries. (18) LOOP_10M TXD[0] corresponds to the first bit to be...
Page 47 PRODUCT OVERVIEW S3C2501X Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet TX_ERR_1/ phob4 Transmit Error/Packet Compression Enable Controller1 PCOMP_10M for 10M. (18) TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY.
Page 48 S3C2501X PRODUCT OVERVIEW Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description Ethernet RX_CLK_1 phis Receive Clock/Receive Clock for 10M. Controller1 RX_CLK is a continuous clock signal. Its (18) frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s.
Page 49 PRODUCT OVERVIEW S3C2501X Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description CUART CURXD phis Console UART Receive Data. CUTXD phob8 Console UART Transmit Data. HUART UCLK Phis HUART External Clock HURXD/GPIO35 phbst8 HUART Receive Data.
Page 50 S3C2501X PRODUCT OVERVIEW Table 1-1. S3C2501X Signal Descriptions (Continue) Group Pin Name Type Pad Type Description HUART HUnCTS/GPIO40 phbst8 Not Clear to send This input pin function controlled by hardware flow control bit value in HUART control register. If hardware flow control bit set to one, HUART can transmit the transmitting data only when this pin state is active.
Page 51: Pad Type
– Open drain buffer Pbusbfs USB Buffer – NOTE: For the detail information about the pad type. Input/Output Cells of the STD130/MDL130 0.18µm 3.3V Standard Cell Library Data Book” which is produced by Samsung Electronics Co., Ltd, ASIC Team. 1-26...
Page 52: Special Registers
S3C2501X PRODUCT OVERVIEW 1.8 SPECIAL REGISTERS Table 1-3. S3C2501X System Configuration Registers Address Description Reset Value SYSCFG 0xF0000000 System configuration register – PDCODE 0xF0000004 Product code and revision number register 0x25010000 CLKCON 0xF0000008 System clock control register 0x00000000 PCLKDIS 0xF000000C...
Page 53 0xF00F0008 Prescaler register 0x00000000 IICCNT 0xF00F000C Prescaler counter register 0x00000000 IICPND 0xF00F0010 Interrupt pending register 0x00000000 Table 1-7. S3C2501X Ethernet Controller 0 Registers Address Description Reset Value BDMATXCONA 0xF00A0000 Buffered DMA transmit control register 0x00000000 BDMARXCONA 0xF00A0004 Buffered DMA receive control register...
Page 54 S3C2501X PRODUCT OVERVIEW Table 1-8. S3C2501X Ethernet Controller 1 Registers Address Description Reset Value BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 BDMATXDPTRB 0xF00C0008 Transmit buffer descriptor start address 0x00000000 BDMARXDPTRB 0xF00C000C...
Page 55 PRODUCT OVERVIEW S3C2501X Table 1-9. S3C2500 DES Controller Registers Address Description Reset Value DESCON 0xF0090000 DES/3DES control register 0×00000000 DESSTA 0xF0090004 DES/3DES status register 0x00000231 DESINT 0xF0090008 DES/3DES interrupt enable register 0x00000000 DESRUN 0xF009000C DES/3DES run enable register 0x00000000 DESKEY1L...
Page 56 S3C2501X PRODUCT OVERVIEW Table 1-10. S3C2501X GDMA Controller Registers Address Description Reset Value DPRIC 0xF0051000 GDMA priority configuration register 0x00000000 DPRIF 0xF0052000 GDMA programmable priority register for fixed 0x00543210 DPRIR 0xF0053000 GDMA programmable priority register for round-robin 0x00000000 DCON0 0xF0050000...
Page 57 Console UART baud rate divisor register 0x0000 CUCHAR1 0xF0060018 Console UART control character register 1 0x00000000 CUCHAR2 0xF006001C Console UART control character register 2 0x00000000 Table 1-12. S3C2501X High speed UART Controller Register Address Description Reset Value HUCON 0xF0080000 High-Speed UART control register 0x00000000 HUSTAT...
Page 58 S3C2501X PRODUCT OVERVIEW Table 1-13. S3C2501X I/O Port Controller Register Address Description Reset Value IOPMODE1 0xF0030000 I/O port mode select register for port 31 to 0 0xF003FFFF IOPMODE2 0xF0030004 I/O port mode select register for port 63 to 32 0xFFFFFFFF...
Page 59 PRODUCT OVERVIEW S3C2501X Table 1-15. S3C2501X Timer Controller Register Address Description Reset Value TMOD 0xF0040000 Timer mode register 0x00000000 0xF0040004 Timer Interrupt Clear 0x00000000 0xF0040008 Watchdog Timer Register 0x00000000 TDATA0 0xF0040010 Timer 0 data register 0x00000000 TCNT0 0xF0040014 Timer 0 count register...
Page 60: Programmer's Model
PROGRAMMER'S MODEL PROGRAMMER′ ′ S MODEL 2.1 OVERVIEW S3C2501X was developed using the advanced ARM9TDMI core designed by advanced RISC machines, Ltd. — Processor Operating States From the programmer′s point of view, the ARM9TDMI can be in one of two states: —...
Page 61: Memory Formats
Word is addressed by byte address of most significant byte. Figure 2-1. Big-Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2-1 in the S3C2501X. Please refer to the chapter 4, system manager. 2.3.2 LITTLE-ENDIAN FORMAT In Little-Endian format, the lowest numbered byte in a word is considered the word′s least significant byte, and...
Page 62: Instruction Length
S3C2501X PROGRAMMER'S MODEL 2.4 INSTRUCTION LENGTH Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 2.5 DATA TYPES ARM9TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four- byte boundaries and half words to two-byte boundaries.
Page 63: Registers
PROGRAMMER'S MODEL S3C2501X 2.7 REGISTERS ARM9TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the programmer.
Page 64: Register Organization In Arm State
S3C2501X PROGRAMMER'S MODEL ARM State General Registers and Program Counter System & User Supervisor About Undefined R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_svc R13_abt R13_irq R13_und R13_fiq R14_svc R14_abt R14_irq R14_und R14_fiq R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
Page 65: Register Organization In Thumb State
PROGRAMMER'S MODEL S3C2501X 2.7.2 The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0–R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR.
Page 66: The Relationship Between Arm And Thumb State Registers
S3C2501X PROGRAMMER'S MODEL 2.7.3 THE RELATIONSHIP BETWEEN ARM AND THUMB STATE REGISTERS The THUMB state registers relate to the ARM state registers in the following way: — THUMB state R0–R7 and ARM state R0–R7 are identical — THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical —...
Page 67: Accessing Hi-Registers In Thumb State
PROGRAMMER'S MODEL S3C2501X 2.7.4 ACCESSING HI-REGISTERS IN THUMB STATE In THUMB state, registers R8–R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.
Page 68: The Condition Code Flags
S3C2501X PROGRAMMER'S MODEL 2.8.1 THE CONDITION CODE FLAGS The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.
Page 69 PROGRAMMER'S MODEL S3C2501X Table 2-1. PSR Mode. Bit Values M[4:0] Mode Visible THUMB State Registers Visible ARM State Registers 10000 User R7..R0, R14..R0, LR, SP PC, CPSR PC, CPSR 10001 R7..R0, R7..R0, LR_fiq, SP_fiq R14_fiq..R8_fiq, PC, CPSR, SPSR_fiq PC, CPSR, SPSR_fiq 10010 R7..R0,...
Page 70: Exceptions
S3C2501X PROGRAMMER'S MODEL 2.9 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.
Page 71: Exception Entry/Exit Summary
PROGRAMMER'S MODEL S3C2501X 2.9.3 EXCEPTION ENTRY/EXIT SUMMARY Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Table 2-2. Exception Entry/Exit Return Instruction Previous State Notes ARM R14_x...
Page 72: Irq
S3C2501X PROGRAMMER'S MODEL 2.9.5 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting the I bit in the CPSR, though this can only be done from a privileged (non-User) mode.
Page 73: Software Interrupt
PROGRAMMER'S MODEL S3C2501X 2.9.7 SOFTWARE INTERRUPT The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): PC,R14_svc This restores the PC and CPSR, and returns to the instruction following the SWI.
Page 74: Exception Priorities
PROGRAMMER′ ′ S MODEL S3C2501X 2.10.1 EXCEPTION PRIORITIES When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6.
Page 75: Interrupt Latencies
PROGRAMMER′ ′ S MODEL S3C2501X 2.11 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser (Tsyncmax if asynchronous), plus the time for the longest instruction to complete (Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort entry (Texc), plus the time for FIQ entry (Tfiq).
Page 76: Introduction For Arm940T
PROGRAMMER′ ′ S MODEL S3C2501X 2.13 INTRODUCTION FOR ARM940T The ARM940T cached processor macrocell is a member of the ARM9 Thumb Family of high-performance 32-bit system-on-a-chip processor solutions. It is targeted at a wide range of embedded control applications where high performance, low system cost, small die size, and low power are key considerations.
Page 77: Arm940T Block Diagram
PROGRAMMER′ ′ S MODEL S3C2501X 2.14 ARM940T BLOCK DIAGRAM CPID[31:0] CPDIN[31:0] CPDOUT[31:0] IA[31:0] DA[31:0] Coprocessor Interface ID[31:0] DD[31:0] Protection Unit I Cache D Cache CP15 Control Control Instruction Data ARM9TDMI Cache Cache Processor Core (Integral EmbeddedICE) JTAG Interface[4:0] AMBA Interface...
Page 78: About The Arm940T Programmer's Model
PROGRAMMER′ ′ S MODEL S3C2501X 2.15 ABOUT THE ARM940T PROGRAMMER'S MODEL The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core, instruction and data caches, a write-buffer, and a protection unit for defining the attributes of regions of memory. The ARM940T incorporates two coprocessors: •...
Page 79: Data Abort Model
PROGRAMMER′ ′ S MODEL S3C2501X 2.15.1 DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI. The difference in the data abort model affects only a very small section of operating system code, the data abort handler.
Page 80: Arm940T Cp15 Registers
PROGRAMMER′ ′ S MODEL S3C2501X 2.16 ARM940T CP15 REGISTERS 2.16.1 CP15 REGISTER MAP SUMMARY The ARM940T incorporates CP15 for system control. The register map for C15 is shown in Table 2-5. Table 2-5. CP15 Register Map Register Function Access ID code/Cache type...
Page 81 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.2 Register 0: Cache type This is a read-only register which allows operating systems to establish how to perform operations such as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.
Page 82 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.3 Register 1: Control register This contains the global control bits of the ARM940T. All reserved bits should either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read.
Page 83 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.4 Register 2: Instruction and data cacheable registers This location provides access to two registers which contain the cacheable attributes for each of eight memory areas. The two registers provide individual control for the I and D address spaces. The opcode_2 field determines whether the instruction-or data-cacheable attributes are programmed: If the opcode_2 field = 0, the data-cacheable bits are programmed.
Page 84 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.5 Register 3: Write buffer control register This register contains a write buffer control (bufferable) attribute bit for each of the eight areas of memory. Each bit is used in conjunction with the cacheable bit to control write-buffer operation.
Page 85 PROGRAMMER′ ′ S MODEL S3C2501X Each register contains the access permission bits, apn[1:0], for the eight areas of instruction or data memory, as shown in Table 2-12. All defined bits in the protection registers are set to zero at reset.
Page 86 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.7 Register 6: Protection region base and size registers This register is used to define 16 programmable regions (eight instruction, eight data) in memory. These registers define the base and size of each of the eight areas of memory. Individual control is provided for the instruction and data memory regions.
Page 87 PROGRAMMER′ ′ S MODEL S3C2501X Each protection region register has the format shown in Table 2-16. Table 2-16. CP15 Protection Region Register Format Register bit Function 31:12 Base address 11:6 Unused Area size (See Table2-17) Region enable. Reset to disable (0).
Page 88 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.8 Register 7: Cache operations A write to this register can be used to perform the following operations: • Flush ICache and Dcache • Prefetch an ICache line • Wait for interrupt • Drain the write buffer •...
Page 89 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.8.1 Index/Segment Format Where the required value is an index/segment, the format is: Table 2-19. CP15 Register 7 Index/Segment Data Format Rd bit position Function 31:26 Index 25:6 Should be zero Segment Should be zero 2.16.1.8.2 ICache Prefetch Data Format...
Page 90 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.8.4 Drain Write Buffer This CP15 operation causes instruction execution to be stalled until the write buffer is emptied. This operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues.
Page 91 PROGRAMMER′ ′ S MODEL S3C2501X 2.16.1.10 Register 15: Test/debug register The DTRRobin and ITRRobin bits set the respective caches into a pseudo round-robin replacement mode. All defined bits in the test registers are set to zero at reset. Table 2-22. CP15 Register 15...
Page 92: Chapter 3 Instruction Set
S3C2501X INSTRUCTION SET INSTRUCTION SET 3.1 INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM9TDMI core. 3.1.1 FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
Page 93: Instruction Summary
INSTRUCTION SET S3C2501X 3.1.2 INSTRUCTION SUMMARY Table 3-1. The ARM Instruction Set Mnemonic Instruction Action Add with carry Rd: = Rn + Op2 + Carry Rd: = Rn + Op2 Rd: = Rn AND Op2 Branch R15: = address Bit clear...
Page 94 S3C2501X INSTRUCTION SET Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action Rd: = Rn OR Op2 Reverse subtract Rd: = Op2 - Rn Reverse subtract with carry Rd: = Op2 - Rn-1 + Carry Subtract with carry Rd: = Rn - Op2-1 + Carry...
Page 95: The Condition Field
INSTRUCTION SET S3C2501X 3.2 THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction′s condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed.
Page 96: Branch And Exchange (Bx)
S3C2501X INSTRUCTION SET 3.3 BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC.
Page 97 INSTRUCTION SET S3C2501X Examples R0, Into_THUMB + 1 ; Generate branch target address ; and set bit 0 high - hence ; arrive in THUMB state. ; Branch and change to THUMB ; state. CODE16 ; Assemble subsequent code as Into_THUMB ;...
Page 98: Branch And Branch With Link (B, Bl)
S3C2501X INSTRUCTION SET 3.4 BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. Cond Offset [24] Link Bit...
Page 99: Assembler Syntax
INSTRUCTION SET S3C2501X 3.4.3 ASSEMBLER SYNTAX Items in {} are optional. Items in < > must be present. B{L}{cond} <expression> Used to request the branch with link form of the instruction. If absent, R14 will not be affected by the instruction.
Page 100: Data Processing
S3C2501X INSTRUCTION SET 3.5 DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-4. 26 25 Opcode Cond Operand2 [15:12] Destination Register...
Page 101 INSTRUCTION SET S3C2501X The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction.
Page 102: Cpsr Flags
S3C2501X INSTRUCTION SET 3.5.1 CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result.
Page 103: Shifts
INSTRUCTION SET S3C2501X 3.5.2 SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right).
Page 104 S3C2501X INSTRUCTION SET Contents of Rm carry out Value of Operand 2 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be specified.
Page 105 INSTRUCTION SET S3C2501X Rotate right (ROR) operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example, ROR #5 is shown in Figure 3-9.
Page 106 S3C2501X INSTRUCTION SET 3.5.2.2 Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output.
Page 107: Immediate Operand Rotates
INSTRUCTION SET S3C2501X 3.5.3 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
Page 108: Instruction Cycle Times
S3C2501X INSTRUCTION SET 3.5.7 INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows: Table 3-4. Incremental Cycle Times Processing Type Cycles Normal data processing Data processing with register specified shift 1S + 1I...
Page 109 INSTRUCTION SET S3C2501X Examples ADDEQ R2,R4,R5 ; If the Z flag is set make R2: = R4 + R5 TEQS R4,#3 ; Test R4 for equality with 3. ; (The S is in fact redundant as the ; assembler inserts it automatically.) R4,R5,R7,LSR R2 ;...
Page 110: Psr Transfer (Mrs, Msr)
S3C2501X INSTRUCTION SET 3.6 PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set.
Page 111: Psr Transfer
INSTRUCTION SET S3C2501X MRS (Transfer PSR Contents to a Register) 00010 001111 Cond 000000000000 [15:21] Destination Register [19:16] Source PSR 0 = CPSR 1 = SPSR_<current mode> [31:28] Condition Field MRS (Transfer Register Contents to PSR) 00010 101001111 Cond 00000000...
Page 112: Reserved Bits
S3C2501X INSTRUCTION SET 3.6.2 RESERVED BITS Only twelve bits of the PSR are defined in ARM9TDMI (N, Z, C, V, I, F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits.
Page 113: Assembler Syntax
INSTRUCTION SET S3C2501X 3.6.4 ASSEMBLER SYNTAX — MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> — MSR - transfer register contents to PSR MSR{cond} <psr>,Rm — MSR - transfer register contents to PSR flag bits only MSR{cond} <psrf>,Rm The most significant four bits of the register contents are written to the N,Z,C &...
Page 114: Multiply And Multiply-Accumulate (Mul, Mla)
S3C2501X INSTRUCTION SET 3.7 MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-12. The multiply and multiply-accumulate instructions use an 8 bit Booth's algorithm to perform integer multiplication.
Page 115: Cpsr Flags
INSTRUCTION SET S3C2501X 3.7.1 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero).
Page 116: Multiply Long And Multiply-Accumulate Long (Mull,Mlal)
S3C2501X INSTRUCTION SET 3.8 MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL,MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-13. The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results.
Page 117: Cpsr Flags
INSTRUCTION SET S3C2501X 3.8.2 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N and Z flags are set correctly on the result (N is equal to bit 63 of the result, Z is set if and only if all 64 bits of the result are zero).
Page 118: Assembler Syntax
S3C2501X INSTRUCTION SET 3.8.4 ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo, RdHi, Rm, Rs Unsigned multiply long 32 x 32 = 64 UMLAL{cond}{S} RdLo, RdHi, Rm, Rs Unsigned multiply & Accumulate long 32 x 32 + 64 = 64...
Page 119: Single Data Transfer (Ldr, Str)
INSTRUCTION SET S3C2501X 3.9 SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
Page 120: Offsets And Auto-Indexing
S3C2501X INSTRUCTION SET 3.9.1 OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn.
Page 121: Little-Endian Offset Addressing
INSTRUCTION SET S3C2501X Memory Register LDR from word aligned address Memory Register LDR from address offset by 2 Figure 3-15. Little-Endian Offset Addressing 3.9.3.2 Big-Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on.
Page 122: Use Of R15
S3C2501X INSTRUCTION SET 3.9.4 USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction.
Page 123: Assembler Syntax
INSTRUCTION SET S3C2501X 3.9.8 ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. If B is present then byte transfer, otherwise word transfer If T is present the W bit will be set in a post-indexed instruction, forcing non- privileged mode for the transfer cycle.
Page 124 S3C2501X INSTRUCTION SET Examples R1,[R2,R4]! ; Store R1 at R2 + R4 (both of which are registers) ; and write back address to R2. R1,[R2],R4 ; Store R1 at R2 and write back R2 + R4 to R2. R1,[R2,#16] ; Load R1 from contents of R2 + 16, but don't write back.
Page 125: Halfword And Signed Data Transfer (Ldrh/Strh/Ldrsb/Ldrsh)
INSTRUCTION SET S3C2501X 3.10 HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16. These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of data.
Page 126: Offsets And Auto-Indexing
S3C2501X INSTRUCTION SET 8 7 6 5 4 3 Cond Offset S H 1 Offset [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfwords 1 1 = Signed byte 1 1 = Signed half words...
Page 127: Half-Word Load And Stores
INSTRUCTION SET S3C2501X 3.10.2 HALF-WORD LOAD AND STORES Setting S = 0 and H = 1 may be used to transfer unsigned Half-words between an ARM9TDMI register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below.
Page 128: Use Of R15
S3C2501X INSTRUCTION SET 3.10.4.2 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bit of the destination register, and the remaining bits of the register are filled with the sign bit, bit 7 of the byte.
Page 129: Assembler Syntax
INSTRUCTION SET S3C2501X 3.10.8 ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> Load from memory into a register Store from a register into memory {cond} Two-character condition mnemonic. See Table 3-2. Transfer half-word quantity Load sign extended byte (Only valid for LDR) Load sign extended half-word (Only valid for LDR) An expression evaluating to a valid register number.
Page 130 S3C2501X INSTRUCTION SET Examples LDRH R1,[R2,-R3]! ; Load R1 from the contents of the half-word address ; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the half-word in R3 at R14+14 but don't write back.
Page 131: Block Data Transfer (Ldm, Stm)
INSTRUCTION SET S3C2501X 3.11 BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers.
Page 132: Addressing Modes
S3C2501X INSTRUCTION SET 3.11.2 ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last.
Page 133: Pre-Increment Addressing
INSTRUCTION SET S3C2501X 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-20. Pre-Increment Addressing 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-21. Post-Decrement Addressing 3-42...
Page 134: Use Of The S Bit
S3C2501X INSTRUCTION SET 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 0x100C 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3-22. Pre-Decrement Addressing 3.11.4 USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction.
Page 135: Inclusion Of The Base In The Register List
INSTRUCTION SET S3C2501X 3.11.6 INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle. A STM which includes storing the base, with the base as the first register to be stored, will therefore store the unchanged value, whereas with the base second or later in the transfer order, will store the modified value.
Page 136: Assembler Syntax
S3C2501X INSTRUCTION SET 3.11.9 ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: {cond} Two character condition mnemonic. See Table 3-2. An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.g. {R0, R2–R7, R10}).
Page 137 INSTRUCTION SET S3C2501X Examples LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{R15} ; R15 <- (SP), CPSR unchanged. LDMFD SP!,{R15}^ ; R15 <- (SP), CPSR <- SPSR_mode ; (allowed only in privileged modes). STMFD R13,{R0-R14}^ ;...
Page 138: Single Data Swap (Swp)
S3C2501X INSTRUCTION SET 3.12 SINGLE DATA SWAP (SWP) Cond 00010 0000 1001 [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field Figure 3-23. Swap Instruction The instruction is only executed if the condition is true.
Page 139: Data Aborts
INSTRUCTION SET S3C2501X 3.12.3 DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either case, the data abort trap will be taken.
Page 140: Software Interrupt (Swi)
S3C2501X INSTRUCTION SET 3.13 SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below 1111 Cond Comment Field (Ignored by Processor) [31:28] Condition Field Figure 3-24.
Page 141: Assembler Syntax
INSTRUCTION SET S3C2501X 3.13.4 ASSEMBLER SYNTAX SWI{cond} <expression> {cond} Two character condition mnemonic, Table 3-2. <expression> Evaluated and placed in the comment field (which is ignored by ARM9TDMI). Examples ReadC ; Get next character from read stream. WriteI+ “k” ; Output a “k” to the write stream.
Page 142: Coprocessor Data Operations (Cdp)
So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2501X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C2501X, the coprocessor instructions are still described here in full for completeness.
Page 143: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.14.3 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle).
Page 144: Coprocessor Data Transfers (Ldc, Stc)
S3C2501X INSTRUCTION SET 3.15 COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-26. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessor's registers directly to memory.
Page 145: Addressing Modes
INSTRUCTION SET S3C2501X 3.15.2 ADDRESSING MODES ARM9TDMI is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and specify byte offsets for single data transfers.
Page 146: Assembler Syntax
S3C2501X INSTRUCTION SET 3.15.7 ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> Load from memory to coprocessor Store from coprocessor to memory When present perform long transfer (N = 1), otherwise perform short transfer (N = 0) {cond} Two character condition mnemonic. See Table 3-2.
Page 147: Coprocessor Register Transfers (Mrc, Mcr)
INSTRUCTION SET S3C2501X 3.16 COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM9TDMI and a coprocessor. An...
Page 148: Transfers To R15
S3C2501X INSTRUCTION SET 3.16.2 TRANSFERS TO R15 When a coprocessor register transfer to ARM9TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
Page 149: Undefined Instruction
INSTRUCTION SET S3C2501X 3.17 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 25 24 5 4 3 xxxxxxxxxxxxxxxxxxxx xxxx Cond Figure 3-28.
Page 150: Instruction Set Examples
S3C2501X INSTRUCTION SET 3.18 INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM9TDMI instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code.
Page 151 INSTRUCTION SET S3C2501X Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross development toolkit, available from your supplier. A short general purpose divide routine follows.
Page 152: Pseudo-Random Binary Sequence Generator
S3C2501X INSTRUCTION SET 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,Ra1 ; Lower accumulate Rh,Rh,Ra2 ; Upper accumulate overflow ; 1 cycle and 2 registers 6. Overflow in signed multiply accumulate with a 64 bit result...
Page 153 INSTRUCTION SET S3C2501X Multiplication by 6 Ra,Ra,Ra,LSL #1 ; Multiply by 3 Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra number Ra,Ra,Ra,LSL#2 ; Multiply by 5 Ra,Rc,Ra,LSL#1 ; Multiply by 2 and add in next digit General recursive method for Rb := Ra*C, C a constant: 1.
Page 154: Loading A Word From An Unknown Alignment
S3C2501X INSTRUCTION SET 3.18.4 LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 Rb,Ra,#3 ; Get word aligned address...
Page 155: Thumb Instruction Set Format
INSTRUCTION SET S3C2501X 3.19 THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets. The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM9TDMI core.
Page 156: Opcode Summary
S3C2501X INSTRUCTION SET 3.19.2 OPCODE SUMMARY The following table summarises the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column. Table 3-7. THUMB Instruction Set Opcodes Mnemonic Instruction Lo-Register...
Page 157 INSTRUCTION SET S3C2501X Table 3-7. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Hi-Register Condition Operand Operand Codes Set Subtract with carry – STMIA Store multiple – – Store word – – STRB Store byte – – STRH Store half-word –...
Page 158: Format 1: Move Shifted Register
S3C2501X INSTRUCTION SET 3.20 FORMAT 1: MOVE SHIFTED REGISTER Offset5 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Figure 3-30. Format 1 3.20.1 OPERATION These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in Table 3-8.
Page 159: Format 2: Add/Subtract
INSTRUCTION SET S3C2501X 3.21 FORMAT 2: ADD/SUBTRACT Rn/Offset3 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Value [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Figure 3-31. Format 2 3.21.1 OPERATION...
Page 160: Instruction Cycle Times
S3C2501X INSTRUCTION SET 3.21.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R0, R3, R4 ;...
Page 161: Format 3: Move/Compare/Add/Subtract Immediate
INSTRUCTION SET S3C2501X 3.22 FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE Offset8 [7:0] Immediate Value [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Figure 3-32. Format 3 3.22.1 OPERATIONS The instructions in this group perform operations between a Lo register and an 8-bit immediate value. The THUMB assembler syntax is shown in Table 3-10.
Page 162: Format 4: Alu Operations
S3C2501X INSTRUCTION SET 3.23 FORMAT 4: ALU OPERATIONS [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode Figure 3-33. Format 4 3.23.1 OPERATION The following instructions perform ALU operations on a Lo register pair. NOTE All instructions in this group set the CPSR condition codes Table 3-11.
Page 163: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.23.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R3, R4 ;...
Page 164: Format 5: Hi-Register Operations/Branch Exchange
S3C2501X INSTRUCTION SET 3.24 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE Rs/Hs Rd/Hd [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode Figure 3-34. Format 5 3.24.1 OPERATION There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed between Lo and Hi registers, or a pair of Hi registers.
Page 165: Instruction Cycle Times
INSTRUCTION SET S3C2501X Table 3-12. Summary of Format 5 Instructions OP H1 THUMB Assembler ARM Equivalent Action ADD Rd, Hs ADD Rd, Rd, Hs Add a register in the range 8-15 to a register in the range 0-7. ADD Hd, Rs...
Page 166: Using R15 As An Operand
S3C2501X INSTRUCTION SET Examples Hi-Register Operations PC, R5 ; PC := PC + R5 but don't set the condition codes.CMP R4, R12 ; Set the condition codes on the result of R4 - R12. R15, R14 ; Move R14 (LR) into R15 (PC) ;...
Page 167: Format 6: Pc-Relative Load
INSTRUCTION SET S3C2501X 3.25 FORMAT 6: PC-RELATIVE LOAD Word 8 [7:0] Immediate Value [10:8] Destination Register Figure 3-35. Format 6 3.25.1 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC. The THUMB assembler syntax is shown below.
Page 168: Format 7: Load/Store With Register Offset
S3C2501X INSTRUCTION SET 3.26 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantity 1 = Transfer byte quantity [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-36.
Page 169: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.26.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-14. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R3, [R2,R6] ;...
Page 170: Format 8: Load/Store Sign-Extended Byte/Half-Word
S3C2501X INSTRUCTION SET 3.27 FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALF-WORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag Figure 3-37. Format 8 3.27.1 OPERATION These instructions load optionally sign-extended bytes or half-words, and store half-words. The THUMB assembler syntax is shown below.
Page 171: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.27.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples...
Page 172: Format 9: Load/Store With Immediate Offset
S3C2501X INSTRUCTION SET 3.28 FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 = Load from memory [12] Byte/Word Flad 0 = Transfer word quantity 1 = Transfer byte quantity Figure 3-38.
Page 173: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.28.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-16. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R2, [R5,#116] ;...
Page 174: Format 10: Load/Store Half-Word
S3C2501X INSTRUCTION SET 3.29 FORMAT 10: LOAD/STORE HALF-WORD Offset5 [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory Figure 3-39. Format 10 3.29.1 OPERATION These instructions transfer half-word values between a Lo register and memory. Addresses are pre-indexed, using a 6-bit immediate value.
Page 175: Format 11: Sp-Relative Load/Store
INSTRUCTION SET S3C2501X 3.30 FORMAT 11: SP-RELATIVE LOAD/STORE Word 8 [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-40. Format 11 3.30.1 OPERATION The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the following table.
Page 176: Format 12: Load Addres
S3C2501X INSTRUCTION SET 3.31 FORMAT 12: LOAD ADDRES Word 8 [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP Figure 3-41. Format 12 3.31.1 OPERATION These instructions calculate an address by adding an 10-bit constant to either the PC or the SP, and load the resulting address into a register.
Page 177: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.31.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-19. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples R2, PC, #572 ;...
Page 178: Format 13: Add Offset To Stack Pointer
S3C2501X INSTRUCTION SET 3.32 FORMAT 13: ADD OFFSET TO STACK POINTER SWord 7 [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative Figure 3-42. Format 13 3.32.1 OPERATION This instruction adds a 9-bit signed constant to the stack pointer. The following table shows the THUMB assembler syntax.
Page 179: Format 14: Push/Pop Registers
INSTRUCTION SET S3C2501X 3.33 FORMAT 14: PUSH/POP REGISTERS Rlist [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-43.
Page 180: Instruction Cycle Times
S3C2501X INSTRUCTION SET 3.33.2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3-21. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. Examples PUSH {R0–R4,LR}...
Page 181: Format 15: Multiple Load/Store
INSTRUCTION SET S3C2501X 3.34 FORMAT 15: MULTIPLE LOAD/STORE Rlist [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory Figure 3-44. Format 15 3.34.1 OPERATION These instructions allow multiple loading and storing of Lo registers. The THUMB assembler syntax is shown in the following table.
Page 182: Format 16: Conditional Branch
S3C2501X INSTRUCTION SET 3.35 FORMAT 16: CONDITIONAL BRANCH Cond SOffset 8 [7:0] 8-bit Signed Immediate [11:8] Condition Figure 3-45. Format 16 3.35.1 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes.
Page 183: Instruction Cycle Times
INSTRUCTION SET S3C2501X Table 3-23. The Conditional Branch Instructions (Continued) Code THUMB ARM Equivalent Action Assembler 1011 BLT label BLT label Branch if N set and V clear, or N clear and V set (less than) 1100 BGT label BGT label...
Page 184: Format 17: Software Interrupt
S3C2501X INSTRUCTION SET 3.36 FORMAT 17: SOFTWARE INTERRUPT Value 8 [7:0] Comment Field Figure 3-46. Format 17 3.36.1 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode.
Page 185: Format 18: Unconditional Branch
INSTRUCTION SET S3C2501X 3.37 FORMAT 18: UNCONDITIONAL BRANCH Offset11 [10:0] Immediate Value Figure 3-47. Format 18 3.37.1 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current instruction.
Page 186: Format 19: Long Branch With Link
S3C2501X INSTRUCTION SET 3.38 FORMAT 19: LONG BRANCH WITH LINK Offset [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low Figure 3-48. Format 19 3.38.1 OPERATION This format specifies a long branch with link.
Page 187: Instruction Cycle Times
INSTRUCTION SET S3C2501X 3.38.2 INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 3-26. The BL Instruction THUMB Assembler ARM Equivalent Action BL label none LR := PC + OffsetHigh << 12 temp := next instruction address PC := LR + OffsetLow <<...
Page 188: Instruction Set Examples
S3C2501X INSTRUCTION SET 3.39 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code. Each example also shows the ARM equivalent so these may be compared. 3.39.1 MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1, 2 or 3 Thumb instructions alongside the ARM equivalents.
Page 189: General Purpose Signed Divide
INSTRUCTION SET S3C2501X 3.39.2 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code. 3.39.2.1 Thumb code ;signed_divide ; Signed divide of R1 by R0: returns quotient in R0, ;...
Page 190 S3C2501X INSTRUCTION SET 3.39.2.2 ARM Code signed_divide ; Effectively zero a4 as top bit will be shifted out later ANDS a4, a1, #&80000000 RSBMI a1, a1, #0 EORS ip, a4, a2, ASR #32 ;ip bit 31 = sign of result ;ip bit 30 = sign of a2...
Page 191: Division By A Constant
INSTRUCTION SET S3C2501X 3.39.3 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code.
Page 192: System Configuration
S3C2501X SYSTEM CONFIGURATION SYSTEM CONFIGURATION 4.1 OVERVIEW The System Configuration consists of several functions that control the clock configuration, system bus arbitration method and address remap function etc. 4.2 FEATURES Key features of the system configuration include the following; •...
Page 193: Address Map
EXT I/O Bank #0 0x00000000 Figure 4-1. S3C2501X Address map after resest Each memory block is mapped within the fixed location of memory space. As shown in the figure 4-1, the maximum size of ROM/SRAM/Flash/External IO bank is restricted to 16M-bytes and the SDRAM bank can be mapped within 1G-byte memory space.
Page 194: Remap Of Memory Space
4.5 EXTERNAL ADDRESS TRANSLATION The S3C2501X address bus is , in some respects, different than the bus used in other standard CPUs. Based on the required data bus width of each memory bank, the internal system address bus is shifted out to an external address bus, ADDR[23:0].
Page 195: Arbitration Scheme
The S3C2501X can support the fixed priority and the round-robin method for AHB bus arbitration by register setting. Especially, the S3C2501X can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode.
Page 196: Priority Groups Of S3C2501X
S3C2501X SYSTEM CONFIGURATION Group A Group B General Group C ARM940T Ethernet Ethernet Controller 0 Controller 1 Figure 4-3. Priority Groups of S3C2501X...
Page 197: Ahb Programmable Priority Registers
The reset value of HPRIR register is 0x00000000. The position for each master is shown in Figure 4-4. The ratio of the bus occupancy of the bus master in the first field is intended to be (hprir0+1)/((hprir2+1)+(hprir1+1)+(hprir0+1)+3) and so on. However, the arbiter of S3C2501X has a fairness problem.
Page 198: Problem Solvings With Programmable Round-Robin
Ethernet controller 0 1/6, and Ethernet controller 1 1/6. In short, GDMA is run four times more than Ethernet controller 0 and 1. This is because S3C2501X is designed to turn the bus occupancy to the next master when there is non-used master. For instance,...
Page 199 SYSTEM CONFIGURATION S3C2501X The following is the problem solving with software. HPRIR Channel Expected Real HPRIR Channel Occupancy System Bus Occupancy Occupancy GDMA GDMA Ethernet Ethernet controller 0 controller 0 ⇒ Ethernet Ethernet controller 1 controller 1 Problem Problem Solving Writing "0x000330", instead of "0x0"...
Page 200: Clock Configuration
4.7 CLOCK CONFIGURATION The S3C2501X has three PLL clocking scheme – CPU PLL, System BUS PLL, PHY PLL. All of the PLL can operate if the corresponding clock select pin is set to “0” (CLKSEL- shared with CPU PLL and System BUS PLL, PHY_CLKSEL).
Page 201 SYSTEM CONFIGURATION S3C2501X Table 4-3. Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins (Continued) CLKMOD [1:0] CPU_FREQ [2:0] BUS_FREQ [2:0] ARM940T Clock AMBA BUS Clock Frequency Frequency 2'b10 (Sync1) 3'b111 3'bxxx 33MHz 16.5MHz 2'b01 (Sync0) 3'b000 3'bxxx 300MHz...
Page 202 S3C2501X SYSTEM CONFIGURATION Table 4-3. Clock Frequencies for CLKMOD Pins, CPU_FREQ Pins, and BUS_FREQ Pins (Continued) CLKMOD [1:0] CPU_FREQ [2:0] BUS_FREQ [2:0] ARM940T Clock AMBA BUS Clock Frequency Frequency 2'b11(Async) 3'b010 3'b000 133MHz 133MHz 3'b010 3'b001 133MHz 133MHz 3'b010 3'b010...
Page 203 Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock. The four PLLs in the S3C2501X are controlled by above formula and the table 4-4 shows the PLL variables for the most widely used frequencies.
Page 204 S3C2501X SYSTEM CONFIGURATION Table 4-4. P, M, S values of the S3C2501X PLL P[5:0] M[7:0] S[1:0] PLL Input Clock PLL Output Clock Frequency Frequency 00_0001 0101_0010 10MHz 300MHz 00_0001 0100_1000 10MHz 266MHz 00_0001 1000_0100 10MHz 233MHz 00_0001 0111_0000 10MHz 200MHz...
Page 205: Shows The Clock Generation Logic Of The S3C2501X
Table 3. The CLKCON[15:0] register can divide the various AMBA clock frequecies of the Table 4-3. All PLL can be controlled by either pin setting or register setting. Figure 4-5. Shows the Clock Generation Logic of the S3C2501X 4-14...
Page 206: System Configuration Special Registers
S3C2501X SYSTEM CONFIGURATION 4.8 SYSTEM CONFIGURATION SPECIAL REGISTERS The System Configuration reigisters are as follows. Table 4-5. System Configuration Registers Name Address Description Reset Value SYSCFG 0xF0000000 System configuration register – PDCODE 0xF0000004 Product code and revision number register 0x25010000...
Page 207: System Configuration Register
SYSTEM CONFIGURATION S3C2501X 4.8.1 SYSTEM CONFIGURATION REGISTER (SYSCFG) You can control the system bus arbitration method, PLL operation, system clock output enable/disable function, external memory address remap function and Little/Big information read function by SYSCFG. Register Address Description Reset Value...
Page 208 S3C2501X SYSTEM CONFIGURATION SYSCFG Description Initial State PPLLFD [24] PPLL Filter Disable This bit determines whether the PHY PLL output is filtered or not during the configuration. When this bit is set to “0”, the PHY PLL output is filtered to be provided to the PHY during the configuration.
Page 209: Product Code And Revision Number Register
SYSTEM CONFIGURATION S3C2501X 4.8.2 PRODUCT CODE AND REVISION NUMBER REGISTER (PDCODE) Register Address Description Reset Value PDCODE 0xF0000004 Product code and revision number register 0x25010000 PDCODE Description Initial State [31-16] Product code 0x2501 Reserved [15:8] Reserved MajRev [7:4] Major revision number...
Page 210: Clock Control Register
S3C2501X SYSTEM CONFIGURATION 4.8.3 CLOCK CONTROL REGISTER (CLKCON) There is clock control register(CLKCON) in system configuration. For the purpose of power save, Clock control register(CLKCON) can be programmed at low frequency and the slower clock than the system clock can be made by clock dividing value.
Page 211: Peripheral Clock Disable Register
SYSTEM CONFIGURATION S3C2501X 4.8.4 PERIPHERAL CLOCK DISABLE REGISTER (PCLKDIS) There is a peripheral clock disable register in system configuration. You can set this register with the specific value for the purpose of power save. If you set PCLKDIS[0] to “1”, the clock for GDMA channel 0 is disabled.
Page 212: Clock Status Register
SYSTEM CONFIGURATION 4.8.5 CLOCK STATUS REGISTER (CLKST) The operating frequency of the S3C2501X can be obtained by reading the CLKST register. The CPU Freq field in CLKST[11:0] decodes the CPU_FREQ[2:0] settings and the BUS Freq in CLKST[23:12] decodes the BUS_FREQ[2:0] settings. There are 3 clock modes in the S3C2501X - fast mode, sync mode and async mode. In async mode, there is no misinformation about the frequency.
Page 213: Core Pll Control Register
SYSTEM CONFIGURATION S3C2501X 4.8.7 CORE PLL CONTROL REGISTER (CPLLCON) If you want to use this register, you should set CPLLREN in SYSCFG[31] to “1”. This register doesn’t work with CPLLREN set to “0”. Register Address Description Reset Value CPLLCON 0xF000001C...
Page 214: System Bus Pll Control Register
S3C2501X SYSTEM CONFIGURATION 4.8.8 SYSTEM BUS PLL CONTROL REGISTER (SPLLCON) If you want to use this register, you should set SPLLREN in SYSCFG[30] to “1”. This register doesn’t work with SPLLREN set to “0”. Register Address Description Reset Value SPLLCON...
Page 215: Phy Pll Control Register
SYSTEM CONFIGURATION S3C2501X 4.8.9 PHY PLL CONTROL REGISTER (PPLLCON) If you want to use this register, you should set PPLLREN in SYSCFG[28] to “1”. This register doesn’t work with PPLLREN set to “0”. Register Address Description Reset Value PPLLCON 0xF0000028...
Page 216: Memory Controller
DMA controller or CPU generates an address that corresponds to a SDRAM bank, the SDRAM controller generates the required SDRAM access signals. • To provide the required signals for bus traffic between the S3C2501X and ROM/SRAM and the external I/O banks. • •...
Page 217: Features
By generating an external bus request, an external device can access the S3C2501X's external memory interface pins. In addition, the S3C2501X can access slow external devices by using a WAIT signal. The WAIT signal, which is generated by the external device, extends the duration of the CPU’s memory...
Page 218: Memory Map
S3C2501X MEMORY CONTROLLER 5.3 MEMORY MAP After a power-on or system reset, all bank address pointer registers are initialized to their default values. And the base address of all banks are fixed. The initial system memory map following system start-up is shown in Figure 5-1.
Page 219: Memory Bank Address Map
Therefore you may connect a SRAM or a Flash Memory with a External I/O Bank. 2. Each EXT I/O bank address is fixed with maximum address range. S3C2501X has 24 address pins, which restrict to 16M-byte address. 3. Each SDRAM bank supports up to 128M-byte in size.
Page 220: Bus Interface Signals
MEMORY CONTROLLER 5.4 BUS INTERFACE SIGNALS The bus interface signals transfer information between the S3C2501X and external memory device. These divide into address and data which used commonly, SDRAM interface signals for SDRAM and memory device interface for ROM/SRAM, etc.
Page 221: Memory Controller Bus Signals
MEMORY CONTROLLER S3C2501X ADDR[23:0] Address & Data DATA[31:0] B0SIZE[1:0] Adjust with pin selection nRCS[7:0] ROM & SRAM nEWAIT/nREADY Interface signals XBMACK External device XBMREQ interface signals S3C2501X nSDWE/nWE16 ROM, SRAM, Flash nWBE/nBE/DQM[3:0] and SDRAM common signals HCLKO nSDCS[1:0] SDRAM Interface...
Page 222: Endian Modes
MEMORY CONTROLLER 5.5 ENDIAN MODES S3C2501X supports both little-endian and big-endian for external memory or I/O devices by setting the pin BIG. Below tables(5-3 through 5-14) are show the program/data path between the CPU register and the external memory using little-/big-endian and word/half-word/byte access.
Page 223 MEMORY CONTROLLER S3C2501X Table 5-5 and 5-6. Using big-endian and half-word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 224 S3C2501X MEMORY CONTROLLER Table 5-7 and 5-8. Using big-endian and byte access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 225 MEMORY CONTROLLER S3C2501X Table 5-9 and 5-10. Using little-endian and word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E...
Page 226 S3C2501X MEMORY CONTROLLER Table 5-11 and 5-12. Using little-endian and half-word access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 227 MEMORY CONTROLLER S3C2501X Table 5-13 and 5-14. Using little-endian and byte access, Program/Data path between register and external memory. WA=Address whose LSB is 0, 4, 8, C, EA=External Address HA=Address whose LSB is 0, 2, 4, 6, 8, A, C, E BA=Address whose LSB is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F X=Don't care.
Page 228: Ext I/O Bank Controller
S3C2501X MEMORY CONTROLLER 5.6 EXT I/O BANK CONTROLLER Ext I/O Bank controller can be interfaceing ROM, SRAM, flash memory, etc, except SDRAM. It also supports muxed bus memory device which shares address bus and data bus. Ext I/O bank controller has three kind of the register for eight banks and then it can be controlled by various timing control options.
Page 229: External Device Connection
MEMORY CONTROLLER S3C2501X 5.6.2 EXTERNAL DEVICE CONNECTION Figure 5-3. illustrates a simple connection between 8-bit ROM/Flash and S3C2501X. ADDR[23:0] ADDR DATA[7:0] DATA 8-bit ROM/ nRCS[0] Flash nWBE[0] S3C2501X Figure 5-3. 8-bit ROM, SRAM and Flash Basic Connection 5-14...
Page 230: Bit Rom, Sram And Flash Basic Connection (8-Bit Memory X 2)
S3C2501X MEMORY CONTROLLER Figure 5-4. illustrates a example connection between two of 8-bit ROM/Flash and S3C2501X for the consisting of 16-bit ROM/SRAM/Flash. ADDR[23:0] ADDR[23:0] DATA[7:0] DATA[7:0] nRCS[0] 8-bit ROM/Flash nWBE[0] S3C2501X ADDR[23:0] DATA[15:8] DATA[7:0] 8-bit ROM/Flash nWBE[1] Figure 5-4. 8-bit ROM, SRAM and Flash Basic Connection (8-bit Memory x 2)
Page 231: Bit Sram Basic Connection
MEMORY CONTROLLER S3C2501X Figure 5-5. illustrates a connection between 16-bit ROM/SRAM and S3C2501X. ADDR[23:0] ADDR DATA[15:0] DATA nSDWE/nWE16 16-bit SRAM nRCS nBE[1] S3C2501X Upper byte nBE[0] Lower byte Figure 5-5. 16-bit SRAM Basic Connection 5-16...
Page 232: Bit Rom And Flash Basic Connection
S3C2501X MEMORY CONTROLLER Figure 5-6. illustrates a connection between 16-bit ROM/Flash and S3C2501X. ADDR[23:0] ADDR DATA[15:0] DATA nRCS 16-bit ROM/Flash nSDWE/nWE16 S3C2501X Figure 5-6. 16-bit ROM and Flash Basic Connection 5-17...
Page 233: Bit Rom Basic Connection 2
MEMORY CONTROLLER S3C2501X Figure 5-7. illustrates a connection between 16-bit ROM and S3C2501X. ADDR[23:0] ADDR DATA[31:0] DATA[15:0] DATA 16-bit ROM nRCS nSDWE/nWE16 S3C2501X ADDR DATA[31:16] DATA 16-bit ROM Figure 5-7. 16-bit ROM Basic Connection 2 5-18...
Page 234: Bit Sram Basic Connection 2
S3C2501X MEMORY CONTROLLER Figure 5-8. illustrates a connection between 16-bit SRAM and S3C2501X. ADDR[23:0] ADDR DATA[31:0] DATA[15:0] DATA 16-bit nRCS SRAM nWBE[1] Upper byte nWBE[0] Lower byte S3C2501X ADDR DATA[31:16] DATA 16-bit SRAM nWBE[3] Upper byte nWBE[2] Lower byte Figure 5-8. 16-bit SRAM Basic Connection 2...
Page 235: Rom & Sram With Muxed Address & Data Bus Connection
MEMORY CONTROLLER S3C2501X Figure 5-9. illustrates a connection between S3C2501X and muxed bus ROM & SRAM. ADDR[23]/ALE DATA[7:0] DATA[7:0] nRCS & nWBE SRAM nWBE S3C2501X nREADY nREADY Figure 5-9. ROM & SRAM with Muxed Address & Data Bus Connection NOTE If the external I/O use nReady signal insteady of nWait, you must select nReady in WAITCON register of memory controller.
Page 236: Ext. I/O Bank Controller Special Register
S3C2501X MEMORY CONTROLLER 5.6.3 EXT. I/O BANK CONTROLLER SPECIAL REGISTER To control the external memory operations, the memory controller uses a dedicated set of special registers (see Table 5-15). By programming the values in the memory controller special registers, you can specify such things as •...
Page 237: Bncon
The Ext I/O Bank controller has eight external I/O access control registers. These registers correspond to up to eight external I/O banks that are supported by S3C2501X. Table 5-16 describes eight registers that are used to control the timing of external I/O bank accesses.
Page 238 S3C2501X MEMORY CONTROLLER Table 5-16. Bank n Control (BnCON) Register Register Address Description Reset Value B0CON 0xF0010000 Bank 0 control register 0xC514E488 (B0SIZE=3) 0x8514E488 (B0SIZE=2) 0x4514E488 (B0SIZE=1) B1CON 0xF0010004 Bank 1 control register 0xC514E488 B2CON 0xF0010008 Bank 2 control register...
Page 239: Bank N Control (Bncon) Register Configuration
MEMORY CONTROLLER S3C2501X 30 29 21 20 TACC TACS TCOS TCOH [3:0] Chip selection hold time on nOE: TCOH 0000 = 0 cycle 0001 = 1 cycle 0010 = 2 cycles 0011 = 3 cycles 0100 = 4 cycles 0101 = 5 cycles 0110 = 6 cycles 0111 = 7 cycles...
Page 240 S3C2501X MEMORY CONTROLLER NOTE 1. If WAITEN of WAITCON register is enable, memory controller can't finish access cycle until nEWAIT signal is high. If you use slow device, you can set WAITEN to '1' and control nEWAIT signal. The memory controller checks nEWAIT signal at the last cycle of TACC. If you set WAITEN to '0', the nEWAIT signal is ignored.
Page 241: Muxed Bus Control (Muxbcon) Register Configuration
MEMORY CONTROLLER S3C2501X 30 29 26 25 21 20 [2-0] Muxed bus address cycle for bank 0: TMA0 001 = 1 cycle 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles...
Page 242 I/O devices are connected to nEWAIT, each WAIT signals of external I/O devices should be or.) nEWAIT is low active signal. When nEWAIT is a low, S3C2501X is waiting until nEWAIT is high again. nREADY in the WAITCON register is used when the external I/O device is ready for transferring data. When nREADY is low, S3C2501X transfers data.
Page 243: Wait Control (Waitcon) Register Configuration
MEMORY CONTROLLER S3C2501X 21 20 Reserved [31:24] Reserved [23] TCOH disable for bank 7: COHDIS7 This forces TCOH to '0' for read to read, write to write, and write to read access in the bank 7 0 = disable 1 = enable...
Page 244: Timing Diagram
S3C2501X MEMORY CONTROLLER 5.6.4 TIMING DIAGRAM HCLKO tRCSd tRCSh tACC nRCS tnOEd tnOEh tADDRd tADDRh ADDR Addr tDATAd tDATAh DATA Data D ata Fetch TACC = 0x8 (8 cycles) TCOS = 0x0 (0 cycle) TCOH = 0x0 (0 cycle) TACS = 0x0 (0 cycle) Figure 5-14.
Page 245: Write Timing Diagram 1
MEMORY CONTROLLER S3C2501X HCLKO tRCSd tRCSh tACC nRCS tnSDWEh tnSDWEd nSDWE tADDRh tADDRd ADDR Addr tDATAd tDATAh DATA Data TACC = 0x8 (8 cycles) TCOS = 0x0 (0 cycle) TCOH = 0x0 (0 cycle) TACS = 0x0 (0 cycle) Figure 5-15. Write Timing Diagram 1...
Page 246: Read Timing Diagram 2
S3C2501X MEMORY CONTROLLER HCLKO tRCSh tRCSd tCOH tACC nRCS tACS tCOS tnOEh tADDRh tADDRd tnOEd ADDR Addr tDATAh tDATAd DATA Data Data Fetch TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TACS = 0x1 (1 cycle) Figure 5-16.
Page 247: Write Timing Diagram 2
MEMORY CONTROLLER S3C2501X HCLKO tRCSd tRCSh tACC tCOH nRCS tACS tCOS tnSDWEd tnSDWEh nSDWE tADDRd tADDRh ADDR Addr tDATAd tDATAh Data DATA TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TACS = 0x1 (1 cycle) Figure 5-17.
Page 248: Read After Write At The Same Bank (Cohdis = 1)
S3C2501X MEMORY CONTROLLER Figure 5-18. Read after Write at the Same Bank (COHDIS = 1) 5-33...
Page 249: Read Timing Diagram (Muxed Bus)
MEMORY CONTROLLER S3C2501X HCLKO tRCSd tRCSh tACC tCOH nRCS tCOS tnOEh tALEd tALEh tnOEd tDATAd tDATAh Addr DATA Data tADDRd tADDRh Data Fetch TACC = 0x4 (4 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TMA = 0x2 (2 cycles) MBE = 1 (Enable) Figure 5-19.
Page 250: Write Timing Diagram (Muxed Bus)
S3C2501X MEMORY CONTROLLER HCLKO tGCSd tGCSh tACC tCOH nRCS tCOS tnSDWEh nSDWE tALEd tALEh tnSDWEd tDATAd tDATAh DATA Addr Data tADDRd tADDRh Data Fetch TACC = 0x4 (4 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x1 (1 cycle) TMA = 0x2 (2 cycles) MBE = 1 (Enable) Figure 5-20.
Page 251: Write Timing Diagram (Newait)
MEMORY CONTROLLER S3C2501X HCLKO tRCSd tRCSh tACC nRCS tACS tCOS tnOEh nSDWE tnOEd ADDR Addr tDATAd tDATAh tADDRd tADDRh DATA Data nEWAIT /nReady tnWAITd tnWAITh TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x0 (0 cycle)
Page 252: Write Timing Diagram (Nready)
S3C2501X MEMORY CONTROLLER HCLKO tRCSd tRCSh tACC nRCS tACS tCOS tnSDWEh nSDWE tnSDWEd ADDR Addr tDATAh tDATAd tADDRd tADDRh DATA Data nEWAIT /nReady tnWAITd tnWAITh TACC = 0x5 (5 cycles) TCOS = 0x1 (1 cycle) TCOH = 0x0 (0 cycle)
Page 253: Sdram Controller
MEMORY CONTROLLER S3C2501X 5.7 SDRAM CONTROLLER 5.7.1 FEATURES The SDRAM controller provides the following features: • Provides merging write buffer to improve system performance. • Supports for 16M-bit, 64M-bit, 128M-bit and 256M-bit SDRAM devices with two or four leaves. •...
Page 254: Sdram Size And Configuration
S3C2501X MEMORY CONTROLLER 5.7.2 SDRAM SIZE AND CONFIGURATION The SDRAM controller supports a SDRAM memory ranging from 2 to 256M-byte. Table 5-19. Illustrates the supported SDRAM configurations when external bus width is 32 bits. Table 5-20. Illustrates the supported SDRAM configurations when external bus width is 16 bits.
Page 255 MEMORY CONTROLLER S3C2501X Table 5-19. Supported SDRAM Configuration of 32-bit External Bus SDRAM SDRAM # Banks Address Size Leaf Select Total Technology Arrangement Memory Size ADDR[14] ADDR[13] (Byte) 16M-bit 2M x 8 – HADDR[21] 16 M 1M x16 – HADDR[21]...
Page 256 S3C2501X MEMORY CONTROLLER Table 5-20. Supported SDRAM Configuration of 16-bit External Bus SDRAM SDRAM # Banks Address Size Leaf Select Total Technology Arrangement Memory Size ADDR[14] ADDR[13] (Byte) 16M-bit 2M x 8 – HADDR[20] 1M x16 – HADDR[20] 64M-bit 8M x 8...
Page 257: Address Mapping
MEMORY CONTROLLER S3C2501X 5.7.3 ADDRESS MAPPING Table 5-21. Illustrates the AHB address bus to the SDRAM address ADDR[14:0] mapping for various memory devices when external bus width is 32 bits. Table 5-22. Illustrates the AHB address bus to the SDRAM address ADDR[14:0] mapping for various memory devices when external bus width is 16 bits.
Page 258 S3C2501X MEMORY CONTROLLER Table 5-22. SDRAM address mapping of 16-bit external bus SDRAM Column Address (AddrOut[14:0]) Technology 16M-bit 2Mx8 1Mx16 64M-bit 8Mx8 4Mx16 128M-bit 16Mx8 8Mx16 256M-bit 32Mx8 16Mx16 SDRAM Row Address (AddrOut[14:0]) Technology 16M-bit 2Mx8 1Mx16 64M-bit 8Mx8 4Mx16...
Page 259: Sdram Commands
MEMORY CONTROLLER S3C2501X 5.7.4 SDRAM COMMANDS The SDRAM controller issues specific commands to the SDRAM devices by encoding the nSDCS, nSDRAS, nSDCAS and nSDWE outputs. Table 5-23. Lists all of the SDRAM commands understood by SDRAM devices. The controller supports a subset of these commands.
Page 260: External Data Bus Width
S3C2501X MEMORY CONTROLLER 5.7.5 EXTERNAL DATA BUS WIDTH The SDRAM controller supports not only 32 bit data bus, but also 16 bit data bus. External data bus width can be selected by the XW field of CFGREG. 5.7.6 MERGING WRITE BUFFER A merging write buffer compacts the writes of all widths into quad-word, which can be efficiently transferred to the SDRAM.
Page 261: Basic Operation
MEMORY CONTROLLER S3C2501X 5.7.8 BASIC OPERATION SDRAM initialization sequence On power-on reset, software must initialize the SDRAM controller and each of the SDRAM connected to the controller. Refer to the SDRAM data sheet for more detailed information on the start up procedure for the SDRAM used.
Page 262: Sdram Special Registers
S3C2501X MEMORY CONTROLLER 5.7.9 SDRAM SPECIAL REGISTERS The address and reset value of the special regsiters in the SDRAM controller summarized in Table 5-24. Table 5-24. SDRAM Special Registers Name Address Description Reset value CFGREG 0xF0020000 Configuration register 0x00099F0C CMDREG...
Page 263 MEMORY CONTROLLER S3C2501X Table 5-25 SDRAM Configuration Register (Continue) Reg0 Description Default value External data bus Width 0 = external bus width is 32 bit. 1 = external bus width is 16 bit. Auto Pre-charge control for SDRAM accesses 0 = Auto pre-charge...
Page 264: Sdram Configuration Register 0
S3C2501X MEMORY CONTROLLER 20 19 12 11 10 9 8 7 6 RESERVED [0] eXternal data bus Width : XW 0 = external bus width is 32 bit ,1 = external bus width is 16 bit [1] Auto Pre-charge control for SDRAM accesses: AP...
Page 265 MEMORY CONTROLLER S3C2501X 5.7.9.2 Command Register The configuration register 1 is 32-bit read/write (some bits are read only) register. The SDRAM initialization command, write buffer operation can be controlled by this register. Table 5-26. SDRAM Command Register Registers Address Description...
Page 266: Sdram Command Register
S3C2501X MEMORY CONTROLLER RESERVED [1:0] Control bits for SDRAM device initialization : 00 = Normal operation 01 = Automatically issue a PALL to the SDRAM 10 = Automatically issue a MRS to the SDRAM 11 = reserved [2] Write buffer enable:...
Page 267: Sdram Refresh Timer Register
MEMORY CONTROLLER S3C2501X 5.7.9.3 Refresh Timer Register The Refresh timer register is 32-bit read/write (some bits are read only) register. This register sets the SDRAM refresh cycle. The refresh timer register is programmed with the number of system bus clock that should be counted between SDRAM refresh cycles.
Page 268: Sdram Write Buffer Time-Out Register
S3C2501X MEMORY CONTROLLER 5.7.9.4 Write Buffer Time-out Register The write buffer time-out register works with the merging write buffer (if write buffer is enabled). This 16-bit read/write field of register sets the cycles for a forced flush of the write buffer.
Page 269: Sdram Controller Timing
MEMORY CONTROLLER S3C2501X 5.7.10 SDRAM CONTROLLER TIMING HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd Row Addr. Col. Addr. ADDR tRDd DATA Data Latency tRDh nSDWE Latency tDQMd DQM/ nWBE tDQMh Row Active Read Figure 5-27. Single Read Operation (CAS Latency=2)
Page 270: Single Read Operation (Cas Latency=3)
S3C2501X MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd ADDR Row Addr. Col. Addr. tRDd DATA Data CAS Latency tRDh nSDWE Latency tDQMd DQM/ nWBE tDQMh Row Active Read Figure 5-28. Single Read Operation (CAS Latency=3)
Page 271: Single Write Operation
MEMORY CONTROLLER S3C2501X HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd Row Addr. Col. Addr. ADDR tWDd Data DATA tWDh tWEd nSDWE tWEh tDQMd DQM / nWBE tDQMh Row Active Write Figure 5-29. Single Write Operation...
Page 272: Burst Read Operation (Cas Latency = 2)
S3C2501X MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tADDRh tCASh tADDRd Row Addr. Col. Addr. ADDR tRDd Data Data Data Data DATA CAS Latency tRDh nSDWE DQM Latency tDQMd DQM/ nWBE tDQMh Row Active Write Figure 5-30.
Page 273: Burst Read Operation (Cas Latency = 3)
MEMORY CONTROLLER S3C2501X HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tCASh tADDRh tADDRd ADDR Col. Addr. Row Addr. tRDd DATA Data Data Data Data tRDh CAS Latency nSDWE DQM Latency tDQMd DQM / nWBE tDQMh Row Active Read Figure 5-31.
Page 274: Burst Write Operation
S3C2501X MEMORY CONTROLLER HCLKO tRCD tCSd nSDCS tCSh tRASd nSDRAS tCASd tRASh nSDCAS tADDRh tCASh tADDRd Row Addr. Col. Addr. ADDR tWDd Data Data Data Data DATA tWEd tWDh nSDWE tWEh tDQMd DQM/ nWBE tDQMh Row Active Write Figure 5-32. Burst Write Operation...
Page 275 MEMORY CONTROLLER S3C2501X NOTES 5-60...
Page 276: Overview
6.2 FEATURES • Supports only single master mode. • Supports 8-bit, bi-directional, serial data transfers. • Supports 7-bit addressing. Figure 6-1 shows a block diagram of the S3C2501X I C controller Data Shift buffer register (IICBUF) Control Serial Serial Clock...
Page 277: Functional Description
C CONTROLLER S3C2501X 6.3 FUNCTIONAL DESCRIPTION The S3C2501X I C controller is the master of the serial I C. Using a prescaler register, the user can program the serial clock frequency that is supplied to the I C controller. The serial clock frequency is calculated as follows: / (16 ×...
Page 278: I 2 C Concepts
S3C2501X C CONTROLLER 6.4 I C CONCEPTS 6.4.1 BASIC OPERATION The I C has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the IC's connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific IC's.
Page 279: General Characteristics
C CONTROLLER S3C2501X Acknowledge Acknowledge from from receiver transmitter SDA by Transmitter SDA by Receiver SCL from Master Stop Start Data Address Condition Condition Figure 6-3. Master Receiver and Slave Transmitter Even in this case, the master IC generates the timing and terminates the transfer.
Page 280: Data Validity
S3C2501X C CONTROLLER 6.4.4 DATA VALIDITY The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when clock signal on the SCL line is low.
Page 281: Data Transfer Operations
C CONTROLLER S3C2501X 6.4.6 DATA TRANSFER OPERATIONS 6.4.6.1 Data Byte Format Every data byte that is put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first.
Page 282: Data Transfer Format
S3C2501X C CONTROLLER 6.4.6.3 Data Transfer Format Data transfers uses the format shown in Figure 6-5. After the start condition has been generated, a 7-bit slave address is sent. The eighth bit is a data direction bit (R/W). A "0" direction bit indicates a transmission (Write) and a "1"...
Page 283: I 2 C Special Registers
C CONTROLLER S3C2501X 6.5 I C SPECIAL REGISTERS The I C controller has three special registers: a control status register (IICCON), a prescaler register (IICPS), and a shift buffer register (IICBUF). 6.5.1 CONTROL STATUS REGISTER (IICCON) The control status register for the I C, IICCON, is described in Table 6-2.
Page 284: I 2 C Control Status Register
S3C2501X C CONTROLLER 6 5 4 3 2 1 Reserved [0] Buffer Flag (BF) 0 = Automatically cleared when the IICBUF register is written or read. To manually clear the BF, write 0. 1 = Automatically set when the buffer is empty in transmit mode or when the buffer is full in receive mode.
Page 285: Shift Buffer Register
C CONTROLLER S3C2501X 6.5.2 SHIFT BUFFER REGISTER (IICBUF) Table 6-3. IICBUF Register Register Address Description Rest Value IICBUF 0xF00F0004 Shift buffer register Undefined Bit Number Bit Name Description [7:0] Data This data field acts as serial shift register and read buffer for interfacing to the I C.
Page 286: Prescaler Counter Register
S3C2501X C CONTROLLER 6.5.4 PRESCALER COUNTER REGISTER (IICCNT) Table 6-5. IICCNT Register Register Address Description Rest Value IICCNT 0xF00F000C Prescaler counter register 0x00000000 Bit Number Bit Name Description [15:0] Counter value This 16-bit value is the value of the prescaler counter. It is read (in test mode only) to check the counter’s current value.
Page 287 C CONTROLLER S3C2501X IIC Setup (Reset, IICPS Setup) IICCON = Start | BF IICBUF = IIC Slave Address | 0x0 IICBUF = IIC Upper Address IICBUF = IIC Lower Address IICBUF = One Byte Data ALL Data Sent? IICCON = Stop Figure 6-7.
Page 288 S3C2501X C CONTROLLER IIC Setup (Reset, IICPS Setup) IICCON = Start | BF IICBUF = IIC Slave Address | 0x0 IICBUF = IIC Upper Address IICBUF = IIC Lower Address IICCON = Repeat Start | ACK IICCON = Start | ACK...
Page 289 C CONTROLLER S3C2501X NOTES 6-14...
Page 290: Chapter 7 Ethernet Controller
ETHERNET CONTROLLER 7.1 OVERVIEW The S3C2501X has two Ethernet controllers that operate at either 100M-bit or 10M-bit per second in half-duplex or full-duplex mode. In half-duplex mode, the IEEE 802.3 carrier sense multiple access with collision detection (CSMA/CD) protocol is supported. In full-duplex mode, the IEEE 802.3 MAC control layer is also supported, including the pause operation for flow control.
Page 291: Features
ETHERNET CONTROLLER S3C2501X 7.2 FEATURES The most important features and benefits of each Ethernet controller are as follows: • Cost-effective connection to an external NIC/Ethernet backbone • Buffered DMA (BDMA) engine with burst mode • BDMA Tx/Rx Buffers (BTxBUFF and BRxBUFF: 256 bytes/256 bytes) •...
Page 292: Mac Function Blocks
S3C2501X ETHERNET CONTROLLER 7.3 MAC FUNCTION BLOCKS The major function blocks of each Ethernet of MAC layer are described in Table 7-1 and Figure 7-1. Table 7-1. MAC Function Block Descriptions Function Block Description Media Independent The interface between the physical layer and the transmit/receiver blocks.
Page 293: Physical Layer Entity (Phy)
ETHERNET CONTROLLER S3C2501X 7.3.2 PHYSICAL LAYER ENTITY (PHY) The physical layer entity, or PHY, performs all of the decoding/encoding on incoming and outgoing data. The manner of decoding and encoding (Manchester for 10BASE-T, 4B/5B for 100BASE-X, or 8B/6T for 100BASE-T4) does not affect the MII.
Page 294 S3C2501X ETHERNET CONTROLLER 7.3.4.5 Threshold Logic and Counters The transmission state machine uses a counter and logic to control the threshold of when the transmission can begin. Before transmitting the MAC waits until eight bytes or a complete frame has been placed in the MTxFIFO.
Page 295: The Mac Receiver Block
ETHERNET CONTROLLER S3C2501X 7.3.5 THE MAC RECEIVER BLOCK It complies with the IEEE802.3 standard for carrier sense multiple access with collision detection (CSMA/CD) protocol. After it receives a frame, the receiver block checks for a number of error conditions: CRC errors, alignment errors, and length errors.
Page 296: Flow Control Block
S3C2501X ETHERNET CONTROLLER 7.3.6 FLOW CONTROL BLOCK Flow control is done using the MAC control frame. The receiver sends control frames to the transmitter and the transmitter pauses its operation during the time interval specified in the control frames. The flow control block provides the following functions: •...
Page 297 ETHERNET CONTROLLER S3C2501X 7.3.7.2 Control and Status This block controls the read/write operations of the bus master across the AMBA. The control logic supports the following operations: — Fixed 4-word burst size control between Tx and Rx. — Transmit threshold control (based on 1/8 of transmit buffer size) to match transmission latency to system bus latency.
Page 298 S3C2501X ETHERNET CONTROLLER 7.3.7.3 Buffer Descriptor The ownership bit in the buffer descriptor controls the owner of the descriptor. When the ownership bit is '1', the BDMA controller owns the descriptor. When the bit is '0', the CPU owns the descriptor. The owner of the descriptor always owns the associated data frame.
Page 299: Data Structure Of Tx Buffer Descriptor
ETHERNET CONTROLLER S3C2501X 18 17 Buffer Pointer TxStatus TxWidget TxLength [31:0] Buffer pointer Address of the data be transmitted. [31] Ownership bit (O) 0 = CPU 1 = BDMA [30:18] TxStatus Writing in this field don't have any mean. [30] Reserved [29] Paused Transmission of frame was paused due to the reception of a Pause control frame.
Page 300: Data Structure Of Rx Buffer Descriptor
S3C2501X ETHERNET CONTROLLER 29 28 27 26 Buffer Pointer B S E D Status RxLength [31:0] Buffer pointer Address of the frame data be saved. [31] Ownership bit (O) 0 = CPU 1 = BDMA [30] Skip BD (B) Set this bit to skip the current buffer descriptor when the ownership bit is cleared.
Page 301: Data Structure Of The Receive Frame
ETHERNET CONTROLLER S3C2501X Buffer Descriptor Start Address Register buffer pointer #1 BRXBDCNT+0 status length buffer #1 BRxBS of BDMARXLEN not used buffer pointer #2 buffer #2 BRXBDCNT+1 status length BRxBS of BDMARXLEN not used buffer #N BRxBS of BDMARXLEN not used...
Page 302: Ethernet Controller Special Registers
S3C2501X ETHERNET CONTROLLER 7.4 ETHERNET CONTROLLER SPECIAL REGISTERS There are two Ethernet controllers in S3C2501X. They are same each other except the base addresses for internal registers. Table 7-2. ETHERNET 0 Special Registers Registers Address Description Reset Value BDMATXCONA 0xF00A0000...
Page 303 ETHERNET CONTROLLER S3C2501X Table 7-3. ETHERNET 1 Special Registers Registers Address Description Reset Value BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 BDMATXDPTRB 0xF00C0008 Transmit buffer descriptor start address 0x00000000 BDMARXDPTRB 0xF00C000C...
Page 304: Bdma Relative Special Register
S3C2501X ETHERNET CONTROLLER 7.4.1 BDMA RELATIVE SPECIAL REGISTER 7.4.1.1 Buffered DMA Transmit Control Register Table 7-4. BDMATXCON Register Registers Address Description Reset Value BDMATXCONA 0xF00A0000 Buffered DMA transmit control register 0x00000000 BDMATXCONB 0xF00C0000 Buffered DMA transmit control register 0x00000000 Bit Number...
Page 305 ETHERNET CONTROLLER S3C2501X 7.4.1.2 Buffered DMA Receive Control Register Table 7-5. BDMA RXCON Register Register Address Description Rest Value BDMARXCONA 0xF00A0004 Buffered DMA receive control register 0x00000000 BDMARXCONB 0xF00C0004 Buffered DMA receive control register 0x00000000 Bit Number Bit Name Description...
Page 306 S3C2501X ETHERNET CONTROLLER 7.4.1.3 BDMA Transmit Buffer Descriptor Start Address Register Table 7-6. BDMATXDPTR Register Registers Address Description Reset Value BDMATXDPTRA 0xF00A0008 BDMA Tx buffer descriptor base register 0x00000000 BDMATXDPTRB 0xF00C0008 BDMA Tx buffer descriptor base register 0x00000000 Bit Number...
Page 307 ETHERNET CONTROLLER S3C2501X 7.4.1.5 BDMA Transmit Buffer Descriptor Counter Table 7-8. BTXBDCNT Register Registers Address Description Reset Value BTXBDCNTA 0xF00A0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer BTXBDCNTB 0xF00C0010 BDMA Tx buffer descriptor counter of Current 0x00000000 Pointer...
Page 308 S3C2501X ETHERNET CONTROLLER 7.4.1.7 BDMA/MAC Transmit Interrupt Enable Register Table 7-10. BMTXINTEN Register Registers Address Description Reset Value BMTXINTENA 0xF00A0018 BDMA/MAC Tx Interrupt Enable 0x00000000 BMTXINTENB 0xF00C0018 BDMA/MAC Tx Interrupt Enable 0x00000000 Bit Number Bit Name Description Enable MAC Tx excessive This bit enables ExColl Interrupt.
Page 309 ETHERNET CONTROLLER S3C2501X 7.4.1.8 BDMA/MAC Transmit Interrupt Status Register Table 7-11. BMTXSTAT Register Registers Address Description Reset Value BMTXSTATA 0xF00A0020 BDMA/MAC Tx Interrupt Status Register 0x00000000 BMTXSTATB 0xF00C0020 BDMA/MAC Tx Interrupt Status Register 0x00000000 Bit Number Bit Name Description Excessive collision (ExColl) This bit is set when collision occurred 16 times consecutively. In this case, the frame transmission is aborted.
Page 310 S3C2501X ETHERNET CONTROLLER 7.4.1.9 BDMA/MAC Receive Interrupt Enable Register Table 7-12. BMRXINTEN Register Registers Address Description Reset Value BMRXINTENA 0xF00A001C BDMA/MAC Rx Interrupt Enable Register 0x00000000 BMRXINTENB 0xF00C001C BDMA/MAC Rx Interrupt Enable Register 0x00000000 Bit Number Bit Name Description Enable MAC Rx missed roll This bit enables MissRoll interrupt.
Page 311 ETHERNET CONTROLLER S3C2501X 7.4.1.10 BDMA/MAC Receive Interrupt Status Register Table 7-13. BMRXSTAT Register Registers Address Description Reset Value BMRXSTATA 0xF00A0024 BDMA/MAC Rx Interrupt Status register 0x00000000 BMRXSTATB 0xF00C0024 BDMA/MAC Rx Interrupt Status register 0x00000000 Bit Number Bit Name Description Missed roll (MissRoll) This bit is set when the missed error counter rolls over.
Page 312 S3C2501X ETHERNET CONTROLLER 7.4.1.11 BDMA Receive Frame Size Register Table 7-14. BDMARXLEN Register Registers Address Description Reset Value BDMARXLENA 0xF00A0028 Receive frame size Undefined BDMARXLENB 0xF00C0028 Receive frame size Undefined Bit Number Bit Name Description [11:0] BDMA Rx Buffer Size...
Page 313: Mac Relative Special Register
ETHERNET CONTROLLER S3C2501X 7.4.2 MAC RELATIVE SPECIAL REGISTER 7.4.2.1 MAC Transmit Control Frame Status The transmit control frame status register, CFTXSTAT provides the status of a MAC control frame as it is sent to a remote station. This operation is controlled by the MSdPause bit in the transmit control register, MACTXCON.
Page 314 S3C2501X ETHERNET CONTROLLER 7.4.2.2 MAC Control Register The MAC control register provides global control and status information for the MAC. The MLINK10 bit is a status bit. All other bits are MAC control bits. MAC control register settings affect both transmission and reception.
Page 315 ETHERNET CONTROLLER S3C2501X 7.4.2.3 CAM Control Register The three acceptance bits (MStation, MGroup, and MBroad) in the CAM control register are used to override the address comparison mode by the compare enable bit(MCompEn). By setting the CAM control register, it is possible to accept frames with all types of destination addresses.
Page 316 S3C2501X ETHERNET CONTROLLER 7.4.2.4 MAC Transmit Control Register Table 7-18. MACTXCON Register Registers Address Description Reset Value MACTXCONA 0xF00B0008 Transmit control 0x00000000 MACTXCONB 0xF00D0008 Transmit control 0x00000000 Bit Number Bit Name Description Transmit enable (MTxEn) Set this bit to enable transmission. To stop transmission immediately, clear the transmit enable bit to '0'.
Page 317 ETHERNET CONTROLLER S3C2501X 7.4.2.5 MAC Transmit Status Register A transmission status flag is set in the transmit status register, MACTXSTAT, whenever the corresponding event occurs. In addition, an interrupt is generated if the corresponding enable bit in the transmit control register is set.
Page 318 S3C2501X ETHERNET CONTROLLER 7.4.2.6 MAC Receive Control Register Table 7-20. MACRXCON Register Registers Offset Description Reset Value MACRXCONA 0xF00B0010 Receive control 0x00000000 MACRXCONB 0xF00D0010 Receive control 0x00000000 Bit Number Bit Name Description Receive enable (MRxEn) Set this bit to '1' to enable MAC receive operation.
Page 319 ETHERNET CONTROLLER S3C2501X 7.4.2.7 MAC Receive Status Register A receive status flag is set in the MAC receive status register, MACRXSTAT, whenever the corresponding event occurs. When a status flag is set, it remains set until another packet arrives, or until software writes a ‘1’ to the flag to clear the status bit.
Page 320 S3C2501X ETHERNET CONTROLLER 7.4.2.8 MAC Station Management Data Register Table 7-22. STADATA Register Registers Address Description Reset Value STADATAA 0xF00B0018 Station management data 0x00000000 STADATAB 0xF00D0018 Station management data 0x00000000 Bit Number Bit Name Description [15:0] Station management data. This register contains a 16-bit data value for the station management function.
Page 321 ETHERNET CONTROLLER S3C2501X 7.4.2.9 MAC Station Management Data Control and Address Register The MAC controller provides support for reading and writing station management data to the PHY. Setting options in station management registers does not affect the controller. Some PHYs may not support the option to suppress preambles after the first operation.
Page 322 S3C2501X ETHERNET CONTROLLER 7.4.2.10 CAM Enable Register The CAMEN register indicates which CAM entries are valid, using a direct comparison mode. Up to 21 entries, numbered 0 through 20, may be active, depending on the CAM size. If the CAM is smaller than 21 entries, the higher bits are ignored.
Page 323 ETHERNET CONTROLLER S3C2501X 7.4.2.11 MAC Missed Error Count Register The value in the missed error count register, MISSCNT, indicates the number of frames that were discarded due to various type of errors. Together with status information on frames transmitted and received, the missed error count register and the two pause count registers provide the information required for station management.
Page 324 S3C2501X ETHERNET CONTROLLER 7.4.2.12 MAC Received Pause Count Register The received pause count register, PZCNT, stores the current value of the 16-bit received pause counter. Table 7-26. PZCNT Register Registers Address Description Reset Value PZCNTA 0XF00B0040 Pause count 0x00000000 PZCNTB...
Page 325 ETHERNET CONTROLLER S3C2501X 7.4.2.14 Content Addressable Memory (CAM) Register There are 21 CAM entries for the destination address and the pause control frame. For the destination address CAM value, one destination address consists of 6 bytes. Using the 32-word space (32 × 4 bytes), you can therefore maintain up to 21 separate destination addresses.
Page 326: Mac Frame Format
S3C2501X ETHERNET CONTROLLER 7.5 ETHERNET OPERATIONS 7.5.1 MAC FRAME FORMAT Table 7-29 lists the eight fields in a standard (IEEE 802.3/Ethernet frame). Table 7-29. MAC Frame Format Description Field Name Field Size Description Preamble 7-byte The bits in each preamble byte are 10101010, transmitted from left to right.
Page 327: Fields Of An Ieee802.3/Ethernet Frame
ETHERNET CONTROLLER S3C2501X Packet (Encoded on the Medium) Data Frame (sent by user) Added by transmitter Added by Transmitter, Stripped by Data frame (delivered to user) Optionaly stripped Receiver by receiver Destination Source Length or Preamble LLC data Address Address...
Page 328 S3C2501X ETHERNET CONTROLLER 7.5.1.2 Destination Address Format Bit 0 of the destination address is an address type designation bit. It identifies the address as either an individual or a group address. Group addresses are sometimes called 'multicast' addresses and individual addresses are called 'unicast' addresses.
Page 329: Csma/Cd Transmit Operation
ETHERNET CONTROLLER S3C2501X The back-off state machine The back-off state machine implements the back-off and retry algorithm of the 802.3 CSMA/CD. When a collision is detected, the main transmission state machine starts the back-off state machine′s counters and waits for the back-off time (including zero) to elapse. This time is a multiple of 512 bit times that elapse before the frame that caused the collision is re-transmitted.
Page 330: Timing For Transmission Without Collision
S3C2501X ETHERNET CONTROLLER The main transmission state machine The main transmission state machine implements the remaining MAC layer protocols. If there is data to be transferred, if the inter-frame gap is valid, and if the MII is ready (that is, if there are no collisions and no CRS in full-duplex mode), the transmitter block then transmits the preamble followed by the SFD.
Page 331: Timing For Transmission With Collision In Preamble
ETHERNET CONTROLLER S3C2501X Tx_clk Tx_en TxD [3:0] Figure 7-8. Timing for Transmission with Collision in Preamble 7.5.1.3.2. BDMA/MAC Interface Operation for Transmission The BDI transmit operation is a simple FIFO mechanism. The BDMA engine stores data to be transmitted, and the transmission state machine empties it when the MAC successfully acquires the net.
Page 332: Receiving Frame Without Error
S3C2501X ETHERNET CONTROLLER 7.5.1.4.1. Receive Frame Timing With/Without Error If, during frame reception, both Rx_DV and Rx_er are asserted, a CRC error is reported for the current packet. As each nibble of the destination address is received, the CAM block attempts to recognize it. After receiving the last destination address nibble, if the CAM block rejects the packet, the receive block asserts the Rx_toss signal, and discards any bytes not yet removed from the receive FIFO that came from the current packet.
Page 333: Csma/Cd Receive Operation
ETHERNET CONTROLLER S3C2501X 7.5.1.4.2 BDMA/MAC Interface Operation for Reception The BDI receive operation is a simple FIFO mechanism. The BDMA engine stores received data to MRxFIFO, and the BDMA RxBUFF controller empties it when the BDMA RxBUFF has enough space left.
Page 334: The Mii Station Manager
S3C2501X ETHERNET CONTROLLER 7.5.2 THE MII STATION MANAGER The MDIO (management data input/output) signal line is the transmission and reception path for control/status information for the station management entity, STA. The STA controls and reads the current operating status of the PHY layer.
Page 335: Full-Duplex Pause Operations
ETHERNET CONTROLLER S3C2501X 7.5.3 FULL-DUPLEX PAUSE OPERATIONS Flow control can be done by the use of control frames. The receive logic in the flow control block recognise a MAC control frame as follows: — The current specification for full-duplex flow control specifies a special destination address for the Pause operation frame.
Page 336 S3C2501X ETHERNET CONTROLLER 7.5.3.1 Transmit Pause Operation To enable a full-duplex Pause operation, the special broadcast address for MAC control frames must be programmed into the CAM, and the corresponding CAM enable bit set. The special broadcast address can be a CAM location.
Page 337: Error Signalling
ETHERNET CONTROLLER S3C2501X 7.5.4 ERROR SIGNALLING The error/abnormal operation flags asserted by the MAC are arranged into transmit and receive groups. These flag groups are located either in the transmit status register (MACTXSTAT) or the receive status register (MACRXSTAT). A missed frame error counter is included for system network management purposes.
Page 338 S3C2501X ETHERNET CONTROLLER 7.5.4.2 Reporting of Reception Errors When it detects a start of frame delimiter (SFD), the MAC starts putting data it has received from the MII into the MRxFIFO. It also checks for internal errors (MRxFIFO overruns) while reception is in progress.
Page 339: Timing Parameters For Mii Transactions
ETHERNET CONTROLLER S3C2501X 7.5.5 TIMING PARAMETERS FOR MII TRANSACTIONS The timing diagrams in this section conform to the guidelines described in the "Draft Supplement to ANSI/IEEE Std. 802.3, Section 22.3, Signal Characteristics." TX_CLK 28ns MIN 4.9ns MIN TXD[3:0] Output Valid TX_EN Figure 7-13.
Page 340: Chapter 8 Des/3Des
The Data Encryption Standard (DES) consists of the Data Encryption Algorithm (DES) and Triple Data Encryption Algorithm (TDEA, as described in ANSI X9.52). The DES/3DES accelerator of the S3C2501X is designed in such a way that they may be used in a computer system or network to provide cryptographic protection to binary coded data.
Page 341: Des/3Des Block Diagram
DES/3DES S3C2501X DES/3DES PWDATA keygen key1 key48 PADDR Register write sig. key2 PENABLE key3 decode PSELx Control in_mode (state left side data sig. machine) PWRITE Status Status PWDATA des_mode left side data desctrl sbox Interrupt wr_indata PRDATA enable in_mode (state left side data sig.
Page 342: Des/3Des Special Registers
S3C2501X DES/3DES 8.3 DES/3DES SPECIAL REGISTERS Table 8-1. DES/3DES Special Registers Overview Registers Address Description Reset Value DESCON 0xF0090000 DES/3DES control register 0×00000000 0x00000231 DESSTA 0xF0090004 DES/3DES status register 0x00000000 DESINT 0xF0090008 DES/3DES interrupt enable register 0x00000000 DESRUN 0xF009000C DES/3DES run enable register...
Page 343: Des/3Des Control Register
DES/3DES S3C2501X 8.3.1 DES/3DES CONTROL REGISTER Table 8-2. DES/3DES Control Register Description Bit Number Bit Name Description Run Enable 0 = DES/3DES disable 1 = DES/3DES enable This bit is the same register as the Run Enable bit of the Run Enable Register.
Page 344: Des/3Des Status Register
S3C2501X DES/3DES 8.3.2 DES/3DES STATUS REGISTER Table 8-3. DES/3DES Status Register Description Bit Number Bit Name Description Idle This bit indicates whether DES/3DES is running or not [3:1] Reserved These bits have 0 value. Available DESINFIFO DESINFIFO is vacant 4 (or 2, depends on DESCON[7]) words or more, this bit is set to 1.
Page 345: Des/3Des Interrupt Enable Register
DES/3DES S3C2501X 8.3.3 DES/3DES INTERRUPT ENABLE REGISTER Table 8-4. DES/3DES Interrupt Enable Register Description Bit Number Bit Name Description Int Idle Interrupt enable register for DES/3DES engine operation 0 = Disable 1 = Interrupt signal is generated when the status register [0] (Idle) bit goes to high which means the end of the current DES/3DES operation.
Page 346: Des/3Des Key 2 Left/Right Side Register
S3C2501X DES/3DES 8.3.6 DES/3DES KEY 2 LEFT/RIGHT SIDE REGISTER Table 8-8. DES/3DES Key 2 Left Side Register Description Bit Number Bit Name Description [1:32] Key 2 Left Half The left half of the Key2 should be stored to this register. The 8 of each byte is parity bit, and it isn't used for encryption/decryption.
Page 347: Des/3Des Input/Output Data Fifo Register
DES/3DES S3C2501X 8.3.9 DES/3DES INPUT/OUTPUT DATA FIFO REGISTER Table 8-14. DES/3DES Input Data FIFO Description Bit Number Bit Name Description [31:0] DESINFIFO This FIFO can be filled by CPU or DMA (depends on control register value). This FIFO consists of 8 words. If data are transferred by DMA, the 4-word burst transaction(DESCON[7] is zero and DCON#[5] is one) is recommended.
Page 348: Des/3Des Operation
S3C2501X DES/3DES 8.4 DES/3DES OPERATION The 64-bit data to be encoded should be written to DESINFIFO of DES/3DES block by CPU or DMA. When the data conversion is completed, the Valid DESOUTFIFO bit in DESSTA is set to 1 and the CPU/DMA can read the encrypted data from the DESOUTFIFO.
Page 349: Performance Calculation Guide
DES/3DES S3C2501X 8.5 PERFORMANCE CALCULATION GUIDE Supposed condition: — DESINFIFO has already data to be encrypting. — DESOUTFIFO can be written data to be encrypted. Cycle Unit (Reference Figure 8-1 DES/3DES Block Diagram) Unit 1: from DESINFIFO to input buffer (1+1/2 cycle)
Page 350: Chapter 9 Gdma Controller
S3C2501X GDMA CONTROLLER GDMA CONTROLLER 9.1 OVERVIEW The S3C2501X has a six-channel General DMA controller, called the GDMA. The six-channel GDMA performs the following data transfers without CPU intervention: • Memory-to-Memory (Memory to/from Memory) • External Device-to-Memory (External Device to/from Memory) •...
Page 351: Gdma Controller Block Diagram
GDMA CONTROLLER S3C2501X AHB BUS Mode Selection GDMA Channel 0 xGDMA_Req0 GDMA_Req GDMA_Ack xGDMA_Ack0 Mode Selection Port 18 Data GDMA Channel 1 xGDMA_Req1 IOPCON1 GDMA_Req GDMA_Ack xGDMA_Ack1 Mode Selection Port 19 Data GDMA Channel 2 xGDMA_Req2 IOPCON1 GDMA_Req GDMA_Ack xGDMA_Ack2...
Page 352: Gdma Special Registers
S3C2501X GDMA CONTROLLER 9.3 GDMA SPECIAL REGISTERS Table 9-1. GDMA Special Registers Overview Registers Address Description Reset Value × DPRIC 0xF0051000 GDMA priority configuration register 00000000 DPRIF 0xF0052000 GDMA programmable priority register for fixed 0x00543210 DPRIR 0xF0053000 GDMA programmable priority register for round-robin 0x00000000 ×...
Page 353: Gdma Programmable Priority Registers
GDMA CONTROLLER S3C2501X 9.3.1 GDMA PROGRAMMABLE PRIORITY REGISTERS The GDMA can support the fixed priority and the round-robin priority for the local arbitration of six GDMA channels by register setting. Especially, the GDMA can program the priority order in the fixed priority mode as well as the ratio of the bus occupancy in the round-robin priority mode.
Page 354: Gdma Programmable Priority Registers
S3C2501X GDMA CONTROLLER DPRIC [0] Priority configuration 0 = Round-robin 1 = Fixed priority DPRIF 12 11 16 15 Reserved dprif5 dprif4 dprif3 dprif2 dprif1 dprif0 Low Priority High Priority DPRIR 16 15 12 11 Reserved dprir5 dprir4 dprir3 dprir2...
Page 355 When DPRIR is 0x0 and only GDMA channel 0, 1, and 2 are used, the expected bus occupancy for each channel is 1/3. However, S3C2501X does not work in that way, instead, GDMA channel 0 gets 4/6 of the bus occupancy, GDMA 1 1/6, and GDMA 2 1/6.
Page 356 S3C2501X GDMA CONTROLLER The following is the problem solving with software. 1. Method 1 DPRIR Channel Expected Real DPRIR Channel Occupancy System Bus Occupancy Occupancy GDMA 0 GDMA 0 GDMA 1 GDMA 1 ⇒ GDMA 2 GDMA 2 Problem Problem Solving by Method 1 Writing "0x000330", instead of "0x0"...
Page 357 GDMA CONTROLLER S3C2501X GDMA Channel Needed Recommended Problem Solving Recommended GDMA Channel Used when S/W 2 Method 2 0, 1, 2, 3, 4, or 5 Method 2 0/3 or 1/4 or 2/5 Method 2 0/2/4 or 1/3/5 Method 1 Method 1...
Page 358: Gdma Control Registers
This bit determines the number of external GDMA requests (xGDMA_Req 0-3) that are required for a GDMA operation. In Single mode, when [4] = "0", the S3C2501X requires an external GDMA request for every GDMA operation. In Block mode, when [4] = "1", the S3C2501X requires only one external GDMA request...
Page 359 GDMA CONTROLLER S3C2501X Table 9-4. GDMA Control Register Description (Continued) Bit Number Bit Name Description Transfer size [7:6] These bits determine the transfer data width to be one byte, one half-word, or one word. If you select a byte transfer operation, the source/destination address will be increased or decreased by one with each transfer.
Page 360: Gdma Control Register
S3C2501X GDMA CONTROLLER 13 12 11 10 9 8 7 6 5 4 RESERVED [0] Run enable (RE) 0 = Disable GDMA operation 1 = Enable GDMA operation [3:1] Mode selection (MODE) 000 = Software mode (Memory to Memory) 001 = External Request mode (for external devices)
Page 361: Gdma Source/Destination Address Registers
0, 1, 2, 3, 4, and 5. These address registers cover the whole external memory space, including the special purpose registers. You have to reference the memory map of the S3C2501X (Chapter 4) when you want to set these address registers. Depending on the settings you make to the GDMA control register (DCON), the source or destination addresses will either remain the same, or they will be increased or decreased.
Page 362: Gdma Transfer Count Registers
S3C2501X GDMA CONTROLLER 9.3.4 GDMA TRANSFER COUNT REGISTERS The GDMA transfer count register indicates the byte transfer rate, which runs at 24-bit, on GDMA channels 0, 1, 2, 3, 4 and 5. Whenever GDMA transfer count register transmits the data of GDMA, it will be diminished by transfer width. In other words, when transfer size (TS) is byte, it will be diminished at 1, in the case of half-word at 2 and word at 4.
Page 363: Gdma Run Enable Registers
GDMA CONTROLLER S3C2501X 9.3.5 GDMA RUN ENABLE REGISTERS The GDMA run enable register (DRER) can enable or disable the RUN ENABLE bit, DCON[0] of the GDMA control register (DCON). The DRER register is write-only register. Table 9-7. DRER0/1/2/3/4/5 Registers Registers...
Page 364: Gdma Interrupt Pending Register
S3C2501X GDMA CONTROLLER 9.3.6 GDMA INTERRUPT PENDING REGISTER The GDMA interrupt pending register (DIPR) indicates the pending state of GDMA interrupt by the pending bit [0] of the DIPR register. The DIPR[0] is active high. The DIPR[0] can be asserted after the GDMA operation completes successfully when the Interrupt Enable field of DCON[12] is "1".
Page 365: Gdma Mode Operation
9.4.3 HUART MODE S3C2501X has one HUART. GDMA channel 3,4,5 can transmit the data of HUART. If GDMA mode selection bit [3:1] to “010” or “011”, GDMA gets ready to communicate with HUART. If GDMA mode is "010" (HUART TX mode) and GDMA receives the request signal transmitted from HUART, GDMA transfers Tx data of HUART in memory into Tx buffer/FIFO of HUART.
Page 366: Des Mode
9.4.4 DES MODE S3C2501X has only one DES. Any channel of GDMA can transmit the data of DES. If GDMA mode selection bit "100" or "101", GDMA gets ready to communicate with DES. If GDMA mode is "100" (DES IN mode) and GDMA receives the request signal transmitted from DES, GDMA transfers IN data of DES in memory into IN buffer/FIFO of DES.
Page 367: Data Transfer Modes
GDMA CONTROLLER S3C2501X 9.5.3 DATA TRANSFER MODES 9.5.3.1 Single Mode A GDMA request (xGDMA_Req or an internal request) causes one byte, one half-word, or one word to be transmitted if four-data burst mode is disabled, or four times of transfer size if four-data burst mode is enabled.
Page 368: Gdma Transfer Timing Data
Figure 9-10 provides the detailed timing data for GDMA data transfers that are triggered by external GDMA requests. Please note that read/write timing depends on which memory banks are selected. The S3C2501X has the internal clock, HCLK, as the operating clock. The clock frequency of HCLK is 133MHz,...
Page 369: Single And One Data Burst Mode
GDMA CONTROLLER S3C2501X 9.6.1 SINGLE AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 0) xGDMA_Req and xGDMA_Ack signals are active high. Recommand deasserted time HCLK xGDMA_Req xGDMA_Ack source dest. Address addr addr source dest. Data...
Page 370: Single And Four Data Burst Mode
S3C2501X GDMA CONTROLLER 9.6.2 SINGLE AND FOUR DATA BURST MODE (DCON[3:1] = 001, [4] = 0, [5] = 1) xGDMA_Req and xGDMA_Ack signals are active high. In four data burst mode, GDMA transfers four data and GDMA Transfer Count Register (DTCR) value decreases by four.
Page 371: Block And One Data Burst Mode
GDMA CONTROLLER S3C2501X 9.6.3 BLOCK AND ONE DATA BURST MODE (DCON[3:1] = 001, [4] = 1, [5] = 0) xGDMA_Req and xGDMA_Ack signals are active high. GDMA transfers data from single xGDMA_Req signal till GDMA Transfer Count Register (DTCR) consumes to 0.
Page 372: Block And Four Data Burst
S3C2501X GDMA CONTROLLER 9.6.4 BLOCK AND FOUR DATA BURST (DCON[3:1] = 001, [4] = 1, [5] = 1) This timing diagram is the same with block and one data burst, except that it is four data burst. Recommand deasserted time...
Page 373 GDMA CONTROLLER S3C2501X NOTES 9-24...
Page 374: Chapter 10 Serial I/O (Console Uart)
SERIAL I/O (CONSOLE UART) 10.1 OVERVIEW The S3C2501X Console UART (Universal Asynchronous Receiver/Transmitter) unit provides one independent asynchronous serial I/O (SIO) port. The port can operate in interrupt-based mode. That is, the Console UART can generate internal interrupts to transfer data between the CPU and the serial I/O port.
Page 375: Console Uart Block Diagram
SERIAL I/O (CONSOLE UART) S3C2501X Transmit Data Register (CUTXBUF) Baud Rate Divisor Transmit Shift Register CUTXD IR Tx Baud Rate Generator Decoder UART Control Register (CUCON) UART Interrupt Enable (CUINT) UART Status Register (CUSTAT) Control Character1,2 (CUCHAR1,2) Receive Data Register...
Page 376: Console Uart Special Registers
S3C2501X SERIAL I/O (CONSOLE UART) 10.3 CONSOLE UART SPECIAL REGISTERS Table 10-1. Console UART Special Registers Overview Register Address Description Size Reset Value CUCON 0xF0060000 Console UART control register 0x00000000 CUSTAT 0xF0060004 Console UART status register 0x00060800 CUINT 0xF0060008 Console UART interrupt enable register...
Page 377: Console Uart Control Registers
SERIAL I/O (CONSOLE UART) S3C2501X 10.3.1 CONSOLE UART CONTROL REGISTERS Table 10-2. CUCON Registers Register Address Description Size Reset Value CUCON 0xF0060000 Console UART control register 0x00000000 Table 10-3. Console UART Control Register Description Bit Number Bit Name Description [1:0]...
Page 378 11 = 8bits [14] Infra-red mode (IR) The S3C2501X Console UART block supports infra-red (IR) transmit and receive operations. In IR mode, the transmit period is pulsed at a rate of 3/16 that of the normal serial transmit rate (when the transmit data value in the CUTXBUF register is zero).
Page 379: Console Uart Control Register
SERIAL I/O (CONSOLE UART) S3C2501X 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [1:0] SIO transmit mode selection (TMODE) 00 = Disable 01 = CPU request 10 = Reserved...
Page 380: Console Uart Control Register
S3C2501X SERIAL I/O (CONSOLE UART) 30 29 28 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [28:15] Reserved (This bit should be cleared) [29] Software Flow Control Enable (SFEN) 0 = Disable Software Flow Control...
Page 381: Console Uart Status Registers
SERIAL I/O (CONSOLE UART) S3C2501X 10.3.2 CONSOLE UART STATUS REGISTERS Table 10-4. CUSTAT Registers Register Address Description Size Reset Value CUSTAT 0xF0060004 Console UART status register 0x00060800 Table 10-5. Console UART Status Register Description Bit Number Bit Name Description Receive Data Valid...
Page 382 S3C2501X SERIAL I/O (CONSOLE UART) Table 10-5. Console UART Status Register Description (Continued) Bit Number Bit Name Description Overrun Error (OER) This bit is automatically set to '1' whenever an overrun error occurs during a serial data receive operation. When CURXBUF has a previous valid data and a new received data is going to be written into CURXBUF, CUSTAT[4] is set to '1'.
Page 383: Console Uart Status Register
SERIAL I/O (CONSOLE UART) S3C2501X 18 17 16 12 11 [0] Receive Data Valid (RDV) 0 = No valid data (Receive FIFO top or CURXBUF) 1 = Valid data present (Receive FIFO top or CURXBUF) [1] Break Signal Deteced (BKD)
Page 384: Console Uart Interrupt Enable Register
S3C2501X SERIAL I/O (CONSOLE UART) 10.3.3 CONSOLE UART INTERRUPT ENABLE REGISTER Table 10-6. CUINT Registers Register Address Description Size Reset Value CUINT 0xF0060008 Console UART interrupt enable register 0x00000000 Table 10-7. Console UART Interrupt Enable Register Description Bit Number Bit Name...
Page 385: Console Uart Interrupt Enable Register
SERIAL I/O (CONSOLE UART) S3C2501X 19 18 17 16 [0] Receive Data Valid Interrupt Enable (RDVIE) [1] Break Signal Detected Interrupt Enable (BKDIE) [2] Frame Error Interrupt Enable (FERIE) [3] Parity Error Interrupt Enable (PERIE) [4] Overrun Error Interrupt Enable (OERIE)
Page 386: Uart Transmit Data Register
S3C2501X SERIAL I/O (CONSOLE UART) 10.3.4 UART TRANSMIT DATA REGISTER Table 10-8. CUTXBUF Registers Register Address Description Size Reset Value CUTXBUF 0xF006000C Console UART transmit data register – Table 10-9. Console UART Transmit Register Description Bit Number Bit Name Description...
Page 387: Uart Receive Data Register
SERIAL I/O (CONSOLE UART) S3C2501X 10.3.5 UART RECEIVE DATA REGISTER Table 10-10. CURXBUF Registers Register Address Description Size Reset Value CURXBUF 0xF0060010 Console UART receive data register – Table 10-11. Console UART Receive Register Description Bit Number Bit Name Description...
Page 388: Uart Baud Rate Divisor Register
S3C2501X SERIAL I/O (CONSOLE UART) 10.3.6 UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers, CUBRD, let you determine the serial TX/RX clock rate (baud rate) as follows: PCLK2 or EXT_UCLK BRGOUT = (CNT0+1) × 16 ×...
Page 389: Console Uart Baud Rate Examples
SERIAL I/O (CONSOLE UART) S3C2501X 10.3.7 CONSOLE UART BAUD RATE EXAMPLES If the system clock frequency is 133 MHz and PCLK2 is selected, the maximum BRGOUT output clock rate is PCLK2/16 (= 4,156,250 Hz). EXT_UCLK is the external clock input pin for Console UART. PCLK2 and EXT_UCLK can be selected by CUCON[5] register.
Page 390: Uart Control Character Register 1 And 2
S3C2501X SERIAL I/O (CONSOLE UART) 10.3.8 UART CONTROL CHARACTER REGISTER 1 AND 2 These Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into these registers. Any character in these registers can be used as a software control flow character and you can use maximum 8 characters for it.
Page 391: Interrupt-Based Serial I/O Transmit And Receive Timing Diagram
SERIAL I/O (CONSOLE UART) S3C2501X <TRANSMIT> Stop Start Data Bits (5-8) Parity Start CUTXD (1-2) INT_TXD <RECEIVE> Stop Start Data Bits (5-8) Parity Start Data Bits CURXD (1-2) INT_RXD Receive Data Receive Data CURXBUF Figure 10-12. Interrupt-Based Serial I/O Transmit and Receive Timing Diagram...
Page 392: Serial I/O Frame Timing Diagram (Normal Console Uart)
S3C2501X SERIAL I/O (CONSOLE UART) SIO Frame Start Stop Data Bits Figure 10-13. Serial I/O Frame Timing Diagram (Normal Console UART) IR Transmit Frame Start Stop Data Bits 3/16T 7/16T 6/16T Bit frame = T Figure 10-14. Infra-Red Transmit Mode Frame Timing Diagram...
Page 393: Infra-Red Receive Mode Frame Timing Diagram
SERIAL I/O (CONSOLE UART) S3C2501X IR Receive Frame Start Stop Data Bits 3/16T Bit frame = T 13/16T Figure 10-15. Infra-Red Receive Mode Frame Timing Diagram 10-20...
Page 394: Overview
FIFO, instead of Tx/Rx buffer register(HUTXBUF/HURXBUF). They are controlled by each FIFO trigger level. The SIO control units provide software controls for mode selection, and for status and interrupt generation. In S3C2501X, software flow control or hardware flow control can be selected according to the application. 11-1...
Page 395: High-Speed Uart Block Diagram
SERIAL I/O (HIGH-SPEED UART) S3C2501X Modem Control Signal Transmit Data TxBuffer Register Transmit Control -------------- Transmit FIFO Transmit Status (32 Bytes) HUART Transmit Shift TX pin Control Register IR Tx Encoder Status Receive Data Block RxBuffer Register Receive Control --------------...
Page 396: High-Speed Uart Special Registers
S3C2501X SERIAL I/O (HIGH-SPEED UART) 11.3 HIGH-SPEED UART SPECIAL REGISTERS Table 11-1. High-Speed UART Special Registers Overview Register Address Description Size Reset Value HUCON 0xF0080000 High-Speed UART control register 0x00000000 HUSTAT 0xF0080004 High-Speed UART status register – HUINT 0xF0080008 High-Speed UART interrupt enable register...
Page 397: High-Speed Uart Control Registers
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.3.1 HIGH-SPEED UART CONTROL REGISTERS Table 11-2. High-Speed UART Control Register Registers Address Description Reset Value HUCON 0xF0080000 High-Speed UART control register 0x00000000 Table 11-3. High-Speed UART Control Register Description Bit Number Bit Name Description...
Page 398 [15] Reserved This bit should be cleared by zero. [16] Transmit FIFO enable S3C2501X High-Speed UART block support 32-byte FIFO. If this bit (TFEN) set to one, transmit data moved to Tx FIFO and then sent. [17] Receive FIFO enable S3C2501X High-Speed UART block support 32-byte FIFO.
Page 399 SERIAL I/O (HIGH-SPEED UART) S3C2501X Table 11-3. High-Speed UART Control Register Description (Continued) Bit Number Bit Name Description [25] Request to Send to pin This bit directly controls the High-Speed UART pin only when the (RTS) High-Speed UART is not hardware flow control mode. If this bit set to one, High-Speed UART pin goes Low level.
Page 400: High-Speed Uart Control Register
S3C2501X SERIAL I/O (HIGH-SPEED UART) 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [1:0] SIO transmit mode selection (TMODE) 00 = Disable 01 = Interrupt request 10 = GDMA request...
Page 401 SERIAL I/O (HIGH-SPEED UART) S3C2501X 30 29 28 27 26 25 23 22 20 19 18 17 16 15 14 13 12 11 8 7 6 [16] Transmit FIFO Enable (TFEN) 0 = Disable Transmit FIFO 1 = Enable Transmit FIFO...
Page 402: High-Speed Uart Status Registers
S3C2501X SERIAL I/O (HIGH-SPEED UART) 11.3.2 HIGH-SPEED UART STATUS REGISTERS Table 11-4. High-Speed UART Status Register Registers Offset Address Description Reset Value HUSTAT 0xF0080004 High-Speed UART status register – Table 11-5. High-Speed UART Status Register Description Bit Number Bit Name...
Page 403 SERIAL I/O (HIGH-SPEED UART) S3C2501X Table 11-5. High-Speed UART Status Register Description (Continued) Bit Number Bit Name Description Overrun Error (OER) This bit automatically set to "1" whenever an overrun error occurs during a serial data receives operation. When HURXBUF has a...
Page 404 S3C2501X SERIAL I/O (HIGH-SPEED UART) Table 11-5. High-Speed UART Status Register Description (Continued) Bit Number Bit Name Description [12] Receive Event time out During Receive FIFO mode, if there is a valid data in HURXFIFO or Receive FIFO within a promised time internal which is determined (E_RxTO) according to WL(Word Length) , this bit is set to '1'.
Page 405: High-Speed Uart Status Register
SERIAL I/O (HIGH-SPEED UART) S3C2501X 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 [0] Receive Data Valid (RDV) 0 = No valid data (Receive FIFO-top or HURXBUF) 1 = Valid data present (Receive FIFO-top or HURXBUF)
Page 406 S3C2501X SERIAL I/O (HIGH-SPEED UART) 18 17 16 10 9 8 7 6 20 19 15 14 13 12 11 [12] Receive Event Time out (E_RxTO) 0 = A promised time is not elapsed during receiving. 1 = Valid data in a promised time...
Page 407: High-Speed Uart Interrupt Enable Register
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.3.3 HIGH-SPEED UART INTERRUPT ENABLE REGISTER Table 11-6. High-Speed UART Interrupt Enable Register Registers Offset Address Description Reset Value HUINT 0xF0080008 High-Speed UART Interrupt Enable register 0x00 Table 11-7. High-Speed UART Interrupt Enable Register Description...
Page 408: High-Speed Uart Interrupt Enable Register
S3C2501X SERIAL I/O (HIGH-SPEED UART) 18 17 16 13 12 11 10 9 8 7 6 [0] Receive Data Valid Interrupt Enable (RDVIE) [1] Break Signal Detected Interrupt Enable (BKDIE) [2] Frame Error Interrupt Enable (FERIE) [3] Parity Error Interrupt Enable (PERIE)
Page 409: High-Speed Uart Transmit Buffer Register
11.3.4 HIGH-SPEED UART TRANSMIT BUFFER REGISTER S3C2501X has a 32-byte Transmit FIFO, and the bottom of FIFO is HUTXBUF. All data to be transmitted are stored into this register at first in FIFO mode, if next buffer has invalid data, then shifted to next buffer. But in non-FIFO mode, a new data to transmit will be moved from HUTXBUF to Tx shift register.
Page 410: High-Speed Uart Receive Buffer Register
11.3.5 HIGH-SPEED UART RECEIVE BUFFER REGISTER S3C2501X has a 32-byte Receive FIFO, and the bottom of FIFO is HURXBUF. All data to be received are stored in this register at first in FIFO mode, if next buffer has invalid data, then shifted to next buffer. But in Non-FIFO mode, a new received data will be moved to HURXBUF.
Page 411: High-Speed Uart Baud Rate Divisor Register
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.3.6 HIGH-SPEED UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers, HUBRD let you determine the serial Tx/Rx clock rate (baud rate) as follows: PCLK2 or EXT_UCLK BRGOUT = (CNT0+1) × 16 ×...
Page 412: High-Speed Uart Baud Rate Examples
S3C2501X SERIAL I/O (HIGH-SPEED UART) 11.3.7 HIGH-SPEED UART BAUD RATE EXAMPLES High-Speed UART BRG input clock, PCLK2 is the system clock frequency divided by 2. If the system clock frequency is 133 MHz and PCLK2 is selected, the maximum BRGOUT output clock rate is PCLK2/16 (= 4,156,250 Hz).
Page 413: High-Speed Uart Control Character 1 Register
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.3.8 HIGH-SPEED UART CONTROL CHARACTER 1 REGISTER This Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into this registers. If not, the reset value will be used as control character. For example, even if you want to use one control character, all control characters will have same value with it.
Page 414: High-Speed Uart Control Character 2 Register
S3C2501X SERIAL I/O (HIGH-SPEED UART) 11.3.9 HIGH-SPEED UART CONTROL CHARACTER 2 REGISTER This Control Character registers can be used for Software Flow control. In Software Flow Control mode, you should write control characters into this registers. If not, the reset value will be used as control character. For example, even if you want to use one control character, all control characters will have same value with it.
Page 415: Autobaud Boundary Register Range
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.3.10 HIGH-SPEED UART AUTOBAUD BOUNDARY REGISTER This autobaud boundary register limit range of each baud rate value that is auto-detected. ABB0 is the lowest boundary value (high baud rate) and ABB3 is the highest value (low baud rate) of autobaud boundary register (actually the highest boundary value is ABT3).
Page 416: High-Speed Uart Autobaud Table Regsiter
S3C2501X SERIAL I/O (HIGH-SPEED UART) 11.3.11 HIGH-SPEED UART AUTOBAUD TABLE REGSITER This autobaud table register corrects each baud rate divisor value that is auto-detected. For detail refer figure 11- 15. If high-speed UART uses external UCLK (29.4912 MHz) and you want to use 460800 baud rate, though high- speed UART detects baud rate divisor register value (CNT0, CNT1) as 0x04, autobaud mechanism will correct baud rate divisor register value as 0x03, because detected value is between 0x05 (ABB1) and 0x02 (ABB0).
Page 417: High-Speed Uart Operation
SERIAL I/O (HIGH-SPEED UART) S3C2501X 11.4 HIGH-SPEED UART OPERATION Data Transmit Operation Flow: If there is no data at Tx Buffer FIFO of High-Speed UART (in case of FIFO, if data in the Tx FIFO are empty as same amount of trigger level), High-Speed UART generates interrupt or GDMA request signal. It depends on High-Speed UART mode.
Page 418: When Cts Signal Level Is High During Transmit Operation
S3C2501X SERIAL I/O (HIGH-SPEED UART) Data Size Start Bit Figure 11-15. When CTS Signal Level is High During Transmit Operation Data Region Start Bit Stop Bit Figure 11-16. When CTS Signal Level is Low During Transmit Operation 11-25...
Page 419: Software Flow Control
SERIAL I/O (HIGH-SPEED UART) S3C2501X Data Region Start Bit Stop Bit Figure 11-17. Normal Received Rx Data Data Region Start Bit Stop Bit Pin Signal Internal Start Bit Signal Figure 11-18. DCD Lost During Rx Data Receive 11.4.3 SOFTWARE FLOW CONTROL Software can control High-Speed UART by control characters.
Page 420: Interrupt-Based Serial I/O Transmit And Receive Timing Diagram
S3C2501X SERIAL I/O (HIGH-SPEED UART) <TRANSMIT> Stop Start Data Bits (5-8) Parity Start TX DATA (1-2) INT_TXD <RECEIVE> Stop Start Data Bits (5-8) Parity Start Data Bits RX DATA (1-2) INT_RXD Receive Data Receive Data HURXBUF Figure 11-19. Interrupt-Based Serial I/O Transmit and Receive Timing Diagram...
Page 421: Dma-Based Serial I/O Timing Diagram (Tx Only)
SERIAL I/O (HIGH-SPEED UART) S3C2501X <TRANSMITTER> TMODE Select DMA Mode Stop TX DATA Start Data Bits (5-8) Parity (1-2) uart_tx_req uart_tx_ack Figure 11-20. DMA-Based Serial I/O Timing Diagram (Tx Only) < RECEIVER > RMODE Select DMA Mode Stop RX DATA...
Page 422: Serial I/O Frame Timing Diagram (Normal High-Speed Uart)
S3C2501X SERIAL I/O (HIGH-SPEED UART) SIO Frame Start Stop Data Bits Figure 11-22. Serial I/O Frame Timing Diagram (Normal High-Speed UART) IR Transmit Frame Start Stop Data Bits 3/16T 7/16T 6/16T Bit frame = T Figure 11-23. Infra-Red Transmit Mode Frame Timing Diagram...
Page 423: Infra-Red Receive Mode Frame Timing Diagram
SERIAL I/O (HIGH-SPEED UART) S3C2501X IR Transmit Frame Start Stop Data Bits 3/16T Bit frame = T 13/16T Figure 11-24. Infra-Red Receive Mode Frame Timing Diagram 11-30...
Page 424: Overview
I/O PORTS 12.1 OVERVIEW S3C2501X has 64 programmable I/O ports. I/O port function control registers (IOPCON2: upper word, IOPCON1: lower word) select either function's port or GPIO. If IOPCON1/2 register is set to GPIO, IOPMODE1/2 register should be set to either input mode or output mode.
Page 425: I/O Port Special Register
I/O PORTS S3C2501X 12.3 I/O PORT SPECIAL REGISTER Table 12-1. I/O Port Special Registers Register Address Description Reset Value IOPMODE1 0xF0030000 I/O port mode select register for port 0 to 31 0xF003FFFF IOPMODE2 0xF0030004 I/O port mode select register for port 32 to 63...
Page 426: I/O Port Mode Registers 1/2
S3C2501X I/O PORTS IOPMODE1 X X X X X IOPMODE2 X X X X X IOPMODE1 IOPMODE2 Signal port Reset value Signal port Reset value GPIO[31] GPIO[63] GPIO[30] GPIO[62] GPIO[29] GPIO[61] GPIO[28] GPIO[60] GPIO[27] GPIO[59] GPIO[26] GPIO[58] GPIO[25] GPIO[57] GPIO[24]...
Page 427: I/O Port Function Control Register
I/O PORTS S3C2501X 12.3.2 I/O PORT FUNCTION CONTROL REGISTER (IOPCON1/2) The I/O port function select registers, IOPCON1/2, are used for function select. IOPCON1/2 are used to configure external interrupt signals, GDMA Req/Ack signals, timer signals and UART Tx/Rx signals. For example, if you set IOPCON1[14] to '0', then port14 is used for GDMA Req port.
Page 428: I/O Function Control Register 1
S3C2501X I/O PORTS Reserved IOPCON1 IOPCON1 Default signal Multiplexed signals (0 / 1) default value GPIO[31] GPIO[31] GPIO[30] GPIO[30] GPIO[29] GPIO[29] GPIO[28] GPIO[28] Timer Output(TOUT)[5] / GPIO[27] GPIO[27] Timer Output(TOUT)[4] / GPIO[26] GPIO[26] Timer Output(TOUT)[3] / GPIO[25] GPIO[25] Timer Output(TOUT)[2] / GPIO[24]...
Page 429: I/O Function Control Register 2
I/O PORTS S3C2501X X X X X X IOPCON2 IOPCON2 Multiplexed signals (0 / 1) Default signal default value GPIO[63] GPIO[63] GPIO[62] GPIO[62] GPIO[61] GPIO[61] GPIO[60] GPIO[60] GPIO[59] GPIO[59] GPIO[58] GPIO[58] GPIO[57] GPIO[57] GPIO[56] GPIO[56] GPIO[55] GPIO[55] GPIO[54] GPIO[54] GPIO[53]...
Page 430: I/O Port Control Register For Gdma
S3C2501X I/O PORTS 12.3.3 I/O PORT CONTROL REGISTER FOR GDMA (IOPGDMA) If the port is used for a function's port such as an external GDMA Req/Ack signal, its signal function is determined by the IOPGDMA register. IOPGDMA register is used to configure GDMA Req/Ack signal. I/O ports provide 3-tap filtering, and you can select filtering on or off.
Page 431: I/O Port Control Register For External Interrupt
I/O PORTS S3C2501X 12.3.4 I/O PORT CONTROL REGISTER FOR EXTERNAL INTERRUPT (IOPEXTINT) If the port is used for a function's port such as an external interrupt request, its signal function is determined by the IOPEXTINT register. IOPEXTINT register is used to configure external interrupt request signals. I/O ports provide 3-tap filtering, and you can select filtering on or off.
Page 432: I/O Port Control Register For External Interrupt
S3C2501X I/O PORTS IOPEXTINT Reserved [23:20] Control external interrupt request5 input for port 13 (xINT5) [23] 0 = active low 1 = active high [22] 0 = filtering off 1 = filtering on [21:20] 00 = level detection 01 = rising edge detection...
Page 433: I/O Port External Interrupt Clear Register
I/O PORTS S3C2501X 12.3.5 I/O PORT EXTERNAL INTERRUPT CLEAR REGISTER (IOPEXTINTPND) External interrupt clear register (IOPEXTINTPND) is set when external interrupt is generated, and you can clear the interrupt status by writing the IOPEXTINTPND status register to '1'. Table 12-6. IOPEXTINTPND Register...
Page 434: I/O Port Data Register
S3C2501X I/O PORTS 12.3.6 I/O PORT DATA REGISTER (IOPDATA1/2) The I/O port data registers, IOPDATA1/2, contain one-bit read values for I/O ports that are configured to input mode and one-bit write values for ports that are configured to output mode.
Page 435 I/O PORTS S3C2501X NOTES 12-12...
Page 436: Overview
INTERRUPT CONTROLLER 13.1 OVERVIEW The S3C2501X interrupt controller has a total of 29 interrupt sources. Interrupt requests can be generated by internal function blocks or external pins. The ARM940T core recognizes two kinds of interrupts: a normal interrupt request (IRQ) and a fast interrupt request (FIQ).
Page 437: Interrupt Sources
INTERRUPT CONTROLLER S3C2501X 13.3 INTERRUPT SOURCES The 29 interrupt sources in the S3C2501X interrupt structure are listed, in brief, as follows: Table 13-1. S3C2501X Internal Interrupt Sources Index Values Interrupt Sources [31] Watchdog Timer interrupt [30] 32-bit Timer 5 interrupt...
Page 438: Interrupt Controller Special Registers
S3C2501X INTERRUPT CONTROLLER Table 13-2. S3C2501X External Interrupt Sources Index Values Interrupt Sources Reserved External interrupt 5 External interrupt 4 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 13.4 INTERRUPT CONTROLLER SPECIAL REGISTERS 13.4.1 INTERRUPT MODE REGISTERS Bit settings in the interrupt mode registers, INTMOD and EXTMOD, specify if an interrupt is to be serviced as a fast interrupt (FIQ) or a normal interrupt (IRQ).
Page 439: Internal Interrupt Mode Register
INTERRUPT CONTROLLER S3C2501X INTMOD [31:0] Internal interrupt mode bits NOTE: Each of the 23 bits in the interrupt mode enable register, INTMOD, corresponds to an interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM940T core in FIQ (fast interrupt) mode.
Page 440: Interrupt Mask Registers
S3C2501X INTERRUPT CONTROLLER EXTMOD [6:0] External interrupt mode bits NOTE: Each of the 6 bits in the external interrupt mode enable register, EXTMOD, corresponds to an external interrupt source. When the source interrupt mode bit is set to 1, the interrupt is processed by the ARM940T core in FIQ (fast interrupt) mode.
Page 441: Internal Interrupt Mask Register
INTERRUPT CONTROLLER S3C2501X INTMASK [31:0] Individual internal interrupt mask bits NOTE: Each of the 23 bits in the interrupt mask register, INTMASK, corresponds to an interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the ARM940T when the corresponding interrupt request is generated.
Page 442: External Interrupt Mask Register
S3C2501X INTERRUPT CONTROLLER EXTMASK [6:0] Individual external interrupt mask bits NOTE: Each of the 6 bits in the external interrupt mask register, EXTMASK, (except for the global mask bit, G) corresponds to an external interrupt source. When a source interrupt mask bit is 1, the interrupt is not serviced by the ARM940T when the corresponding interrupt request is generated.
Page 443: Interrupt Priority Registers
INTERRUPT CONTROLLER S3C2501X 13.4.3 INTERRUPT PRIORITY REGISTERS The interrupt priority registers, INTPRIOR0–INTPRIOR9, contain information about which interrupt source is assigned to the pre-defined interrupt priority field. Each INTPRIORn register value determines the priority of the corresponding interrupt source. The lowest priority value is 0x0, and the highest priority value is 0x26.
Page 444: Interrupt Offset Register
S3C2501X INTERRUPT CONTROLLER 13.4.4 INTERRUPT OFFSET REGISTER The interrupt offset registers, INTOFFSET_FIQ and INTOFFSET_IRQ, contain the interrupt offset address of the interrupt, which has the highest priority among the pending interrupts. The content of the interrupt offset address is "index value of the interrupt source”.
Page 445 INTERRUPT CONTROLLER S3C2501X Table 13-7. Index Value of Interrupt Sources Index Value Type of Interrupt Sources Returned Default Offset Value (Hex) [38] Watchdog Timer interrupt 0 x 26 [37] 32 bit Timer 5 interrupt 0 x 25 [36] 32 bit Timer 4 interrupt...
Page 446 S3C2501X INTERRUPT CONTROLLER Table 13-7. Index Value of Interrupt Sources (Continued) Index Value Type of Interrupt Sources Returned Default Offset Value (Hex) Reserved Reserved Reserved Reserved IIC interrupt 0 x 7 Reserved Reserved External interrupt 5 0 x 5 External interrupt 4...
Page 447: Interrupt By Priority Register
INTERRUPT CONTROLLER S3C2501X 13.4.5 INTERRUPT BY PRIORITY REGISTER The interrupt by priority registers, IPRIORHI and IPRIORLO, contain interrupt pending bits, which are re-ordered by the INTPRIORn register settings. IPRIORLO[13] is mapped to the interrupt source of whichever bit index is written into the priority 13 field of the INTPRIORn registers.
Page 448: Overview
S3C2501X 32-BIT TIMERS 32-BIT TIMERS 14.1 OVERVIEW The timer has six 32-bit timers and one watchdog timer. Six 32-bit timers have Timer Mode register (TMOD) which is used to control the operation of the six 32-bit timers, Timer Data registers (TDATAn) which are data registers for counting, Timer Count registers (TCNTn) which are count value registers, and Timer Interrupt Clear register (TIC) which is used to clear the current interrupt.
Page 449: Interval Mode Operation
32-BIT TIMERS S3C2501X 14.3 INTERVAL MODE OPERATION In interval mode, a timer generates one-shot pulse of preset timer clock duration whenever a time-out occurs. This pulse generates a time-out interrupt that is directly output at the timer's configured output pin (TOUTn). In...
Page 450: Timer Operation Guidelines
32-BIT TIMERS 14.5 TIMER OPERATION GUIDELINES The block diagram in Figure 14-2 shows how the 32-bit timers are configured in the S3C2501X. The following guidelines apply to the timer functions. When a timer is enabled, it loads a data value (TDATA) to its count register (TCNT) and begins decrement of the count register value (TCNT).
Page 451: Timer Mode Register
32-BIT TIMERS S3C25 14.6.1 TIMER MODE REGISTER The timer mode register, TMOD, is used to control the operation of the six 32-bit timers. Table 14-1. TMOD Register Register Description TMOD 0xF0040000 Timer mode register 0x00000000 14-4...
Page 452: Timer Mode Register
S3C2501X 32-BIT TIMERS [0] Timer 0 enable (TE0) [9] Timer 3 enable (TE3) 0 = Disable timer 0 0 = Disable timer 3 1 = Enable timer 0 1 = Enable timer 3 [1] Timer 0 mode selection (TMD0) [10] Timer 3 mode selection (TMD3)
Page 453: Timer Data Registers
32-BIT TIMERS S3C2501X 14.6.2 TIMER DATA REGISTERS The timer data registers, TDATA0 - TDATA5, contain a value that specifies the time-out duration for each timer. The formula for calculating the time-out duration is: (Timer data) cycles. The timer is dependent on the system bus clock. When the system bus is 133 MHz, the minimum value, 0x1 for TDATA, generates interrupt at every 7.5n sec.
Page 454: Timer Count Registers
32-BIT TIMERS The timer count registers, TCNT0 - TCNT5, contain the current timer 0 - 5 count value, respectively, during the normal operation. Register Address Description Reset Value 0xF0040014 0xFFFFFFFF TCNT1 Timer 1 count register TCNT2 0xF0040024 Timer 2 count register 0xFFFFFFFF 0xF004002C 0xFFFFFFFF...
Page 455: Timer Interrupt Clear Registers
32-BIT TIMERS S3C2501X 14.6.4 TIMER INTERRUPT CLEAR REGISTERS Timer Interrupt Clear register (TIC) clears the current interrupt of the six 32-bit timers and one watchdog timer. Table 14-4. Timer Interrupt Clear Registers Register Address Description Reset Value 0xF0040004 Timer Interrupt Clear...
Page 456: Watchdog Timer Register
S3C2501X 32-BIT TIMERS 14.6.5 WATCHDOG TIMER REGISTER (WDT) To use Watchdog Timer, Watchdog Timer Register (WDT) must be set. If WDT[29] (RST) is ‘1’ when WDT[31] (EN) was asserted, the timeout counter in watchdog timer is cleared as ‘0’. Following this cycle, WDT[29] (RST) is automatically deasserted.
Page 457 32-BIT TIMERS S3C2501X Table 14-6. Watchdog Timer Timeout Value (WDTVAL, X: Don't Care) (When watchdog timer operates at 133 MHz) No Operation (3.8us) (30.7us) (245.8us) (491.5us) (983.0us) (1.97ms) (3.93ms) (7.86ms) (15.72ms) (31.45ms) (62.91ms) (125.82ms) (251.65ms) (503.31ms) (1.00s) (2.01s) (4.02s) (8.05s)
Page 458: Overview
S3C2501X ELECTRICAL DATA ELECTRICAL DATA 15.1 OVERVIEW This chapter describes the S3C2501X electrical data. 15.2 ABSOLUTE MAXIMUM RATINGS Table 15-1. Absolute Maximum Ratings Symbol Parameter Rating Unit 1.8V V DC supply voltage 3.3V V DC input voltage 3.3V input buffer DC output voltage 3.3V input buffer...
Page 459: Dc Electrical Specifications
ELECTRICAL DATA S3C2501X 15.4 DC ELECTRICAL SPECIFICATIONS = -40 to 85 C Symbol Condition Unit High level input voltage LVCMOS interface – Low level input voltage – – Switching threshold Schmitt trigger, positive-going CMOS – Schmitt trigger, negative- CMOS –...
Page 460 S3C2501X ELECTRICAL DATA Table 15-3. D.C Electric Characteristics (Continued) Symbol PARAMETER Condition Type Unit Low level output voltage = 1 µA Type B1 to B12 – – 0.05 = 1 mA Type B1 = 2 mA Type B2 = 4 mA...
Page 461: Ac Electrical Characteristics
ELECTRICAL DATA S3C2501X 15.5 AC ELECTRICAL CHARACTERISTICS Table 15-4. Operating Frequency Characteristic Units Core frequency System bus frequency USB Frequency Table 15-5. Clock AC timing specification Characteristic Units µs Internal PLL lock time – Frequency of operation (XCLK) – XCLK cycle time –...
Page 462 S3C2501X ELECTRICAL DATA Table 15-6. AC Electrical Characteristics for S3C2501X Signal Name Description Unit tnRCSd ROM/SRAM chip select delay time 1.32 3.43 tnRCSh ROM/SRAM chip select hold time 1.17 3.02 tnOEd ROM/SRAM output enable delay time 0.79 1.93 tnOEh ROM/SRAM output enable hold time 0.69...
Page 463 ELECTRICAL DATA S3C2501X NOTES 15-6...
Page 464: Overview
S3C2501X MECHANICAL DATA MECHANICAL DATA 16.1 OVERVIEW The S3C2501X is available in a 272-pin BGA package (272-BGA-2727-AN). 16-1...
Page 465: Bga-2727-An Package Dimensions
MECHANICAL DATA S3C2501X ± 0.10 27.00 ± 0.10 24.00 272-BGA-2727-AN 0.15 MAX 1.27 272-φ 0.76 ± 0.015 φ 0.38 MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 18 19 20 Figure 16-1.

Samsung S3C2501X User Manual

Chapter 1 Product Overview

Chapter 2 Programmer's Model

Chapter 3 Instruction Set

Chapter 4 System Configuration

Chapter 5 Memory Controller

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